[llvm] [ARM] Add pass for handling undef early-clobber values (PR #77770)
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Wed Jan 24 01:56:27 PST 2024
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 0ed8194256c6c96875ed9dd102d15ee8a9260fec 7148a248d4baf2c413a569038cad82c8fa6f813d -- llvm/include/llvm/CodeGen/Passes.h llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/include/llvm/CodeGen/TargetSubtargetInfo.h llvm/include/llvm/InitializePasses.h llvm/lib/CodeGen/TargetPassConfig.cpp llvm/lib/Target/ARM/ARMAsmPrinter.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.h llvm/lib/Target/ARM/ARMSubtarget.h llvm/lib/Target/RISCV/RISCV.h llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp llvm/lib/CodeGen/InitUndef.cpp
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View the diff from clang-format here.
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diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 80c7b79e01..5dffe46345 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2229,13 +2229,14 @@ public:
llvm_unreachable("Unexpected register class.");
}
- virtual const TargetRegisterClass *getVRLargestSuperClass(const TargetRegisterClass *RC) const {
+ virtual const TargetRegisterClass *
+ getVRLargestSuperClass(const TargetRegisterClass *RC) const {
llvm_unreachable("Unexpected target register class.");
}
virtual bool isVectorRegClass(const TargetRegisterClass *RC) const {
- llvm_unreachable("Unexpected Register or MachineRegisterInfo");
-}
+ llvm_unreachable("Unexpected Register or MachineRegisterInfo");
+ }
virtual unsigned getNoRegisterValue() const {
llvm_unreachable("Unexpected target register class.");
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 929176998d..ba6af1ea44 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -301,7 +301,7 @@ void initializeTLSVariableHoistLegacyPassPass(PassRegistry &);
void initializeTwoAddressInstructionPassPass(PassRegistry&);
void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
void initializeTypePromotionLegacyPass(PassRegistry&);
-void initializeInitUndefPass(PassRegistry&);
+void initializeInitUndefPass(PassRegistry &);
void initializeUniformityInfoWrapperPassPass(PassRegistry &);
void initializeUnifyLoopExitsLegacyPassPass(PassRegistry &);
void initializeUnpackMachineBundlesPass(PassRegistry&);
diff --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index c358ca49c4..5aa7bbc8a1 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -127,7 +127,7 @@ bool InitUndef::handleReg(MachineInstr *MI) {
}
bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
- const DeadLaneDetector &DLD) {
+ const DeadLaneDetector &DLD) {
bool Changed = false;
for (MachineOperand &UseMO : MI.uses()) {
@@ -191,8 +191,9 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
LLVM_DEBUG(
- dbgs() << "Emitting PseudoInitUndef Instruction for implicit vector register "
- << MO.getReg() << '\n');
+ dbgs()
+ << "Emitting PseudoInitUndef Instruction for implicit vector register "
+ << MO.getReg() << '\n');
const TargetRegisterClass *TargetRegClass =
TII->getVRLargestSuperClass(MRI->getRegClass(MO.getReg()));
@@ -205,9 +206,8 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
return true;
}
-bool InitUndef::processBasicBlock(MachineFunction &MF,
- MachineBasicBlock &MBB,
- const DeadLaneDetector &DLD) {
+bool InitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
+ const DeadLaneDetector &DLD) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
MachineInstr &MI = *I;
@@ -219,13 +219,13 @@ bool InitUndef::processBasicBlock(MachineFunction &MF,
MachineOperand &UseMO = MI.getOperand(UseOpIdx);
if (UseMO.getReg() == TII->getNoRegisterValue()) {
const TargetRegisterClass *RC =
- TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
+ TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
Register NewDest = MRI->createVirtualRegister(RC);
// We don't have a way to update dead lanes, so keep track of the
// new register so that we avoid querying it later.
NewRegs.insert(NewDest);
- BuildMI(MBB, I, I->getDebugLoc(),
- TII->get(TargetOpcode::IMPLICIT_DEF), NewDest);
+ BuildMI(MBB, I, I->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF),
+ NewDest);
UseMO.setReg(NewDest);
Changed = true;
}
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 14bdf5db18..8e39e51a28 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -2414,7 +2414,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
return;
}
-
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 02e6b6a8a7..a5ca891984 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -541,13 +541,14 @@ public:
Register Reg) const override;
unsigned getUndefInitOpcode(unsigned RegClassID) const override {
- if(RegClassID == ARM::MQPRRegClass.getID()){
+ if (RegClassID == ARM::MQPRRegClass.getID()) {
return ARM::PseudoARMInitUndef;
}
- llvm_unreachable("Unexpected register class.");
+ llvm_unreachable("Unexpected register class.");
}
- const TargetRegisterClass *getVRLargestSuperClass(const TargetRegisterClass *RC) const override {
+ const TargetRegisterClass *
+ getVRLargestSuperClass(const TargetRegisterClass *RC) const override {
if (ARM::MQPRRegClass.hasSubClassEq(RC))
return &ARM::MQPRRegClass;
return RC;
@@ -557,9 +558,7 @@ public:
return ARM::MQPRRegClass.hasSubClassEq(RC);
}
- unsigned getNoRegisterValue() const override{
- return ARM::NoRegister;
- }
+ unsigned getNoRegisterValue() const override { return ARM::NoRegister; }
};
/// Get the operands corresponding to the given \p Pred value. By default, the
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 43eee8b8c6..14c4ee6e8b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -264,7 +264,8 @@ public:
ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
getSerializableMachineMemOperandTargetFlags() const override;
- const TargetRegisterClass * getVRLargestSuperClass(const TargetRegisterClass *RC) const override{
+ const TargetRegisterClass *
+ getVRLargestSuperClass(const TargetRegisterClass *RC) const override {
if (RISCV::VRM8RegClass.hasSubClassEq(RC))
return &RISCV::VRM8RegClass;
if (RISCV::VRM4RegClass.hasSubClassEq(RC))
@@ -278,9 +279,9 @@ public:
bool isVectorRegClass(const TargetRegisterClass *RC) const override {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
- RISCV::VRM2RegClass.hasSubClassEq(RC) ||
- RISCV::VRM4RegClass.hasSubClassEq(RC) ||
- RISCV::VRM8RegClass.hasSubClassEq(RC);
+ RISCV::VRM2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRM4RegClass.hasSubClassEq(RC) ||
+ RISCV::VRM8RegClass.hasSubClassEq(RC);
}
unsigned getUndefInitOpcode(unsigned RegClassID) const override {
@@ -298,9 +299,7 @@ public:
}
}
- unsigned getNoRegisterValue() const override {
- return RISCV::NoRegister;
- }
+ unsigned getNoRegisterValue() const override { return RISCV::NoRegister; }
protected:
const RISCVSubtarget &STI;
``````````
</details>
https://github.com/llvm/llvm-project/pull/77770
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