[llvm] GlobalISel needs fdiv 1 / sqrt(x) to rsq combine (PR #78673)

[Pierre van Houtryve via llvm-commits]

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@@ -0,0 +1,80 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
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Pierre-vh wrote:

add some more types (f32/f64) - you can just copy-paste the f16/neg_f16 test for those types

https://github.com/llvm/llvm-project/pull/78673