[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via llvm-commits]

================
@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands(
   if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())
     return false;
 
+  // Don't sink splat operands if the target prefers it. Some targets requires
----------------
michaelmaitland wrote:

I took the changes out of this patch. I will work on the next patch once this lands since there are a few fixups here and it will be easier to work off the squashed commit.

https://github.com/llvm/llvm-project/pull/79015