[llvm] [X86] X86FixupVectorConstants - shrink vector load to movsd/movsd/movd/movq 'zero upper' instructions (PR #79000)

[Simon Pilgrim via llvm-commits]

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@@ -47,10 +47,10 @@ define i32 @PR63108() {
 ; AVX1-NEXT:    testb %al, %al
 ; AVX1-NEXT:    je .LBB0_2
 ; AVX1-NEXT:  # %bb.1:
-; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm0 = [251,223,0,0,251,223,0,0,251,223,0,0,251,223,0,0]
+; AVX1-NEXT:    vmovd {{.*#+}} xmm0 = [57339,0,0,0]
 ; AVX1-NEXT:    jmp .LBB0_5
 ; AVX1-NEXT:  .LBB0_2: # %vector.body.preheader
-; AVX1-NEXT:    vmovaps {{.*#+}} xmm0 = [57339,0,0,0]
+; AVX1-NEXT:    vmovss {{.*#+}} xmm0 = [57339,0,0,0]
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RKSimon wrote:

the movaps/movss is due to AVX1 only having fp-ops on the 256-bit code below

https://github.com/llvm/llvm-project/pull/79000