[llvm] [RISCV] Exploit register boundaries when lowering shuffle with exact vlen (PR #79072)

[Craig Topper via llvm-commits]

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@@ -4699,7 +4696,8 @@ static SDValue lowerShuffleViaVRegSplitting(ShuffleVectorSDNode *SVN,
       // less an implementation question, and more a profitability one.
       return SDValue();
 
-    OutMasks[DstVecIdx].second.resize(ElemsPerVReg);
+    if (OutMasks[DstVecIdx].second.empty())
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topperc wrote:

I think you could use `resize(ElemsPerVReg, -1)`. The second argument is only used if the size increases.

https://github.com/llvm/llvm-project/pull/79072