[llvm] [RISCV] Allow VCIX with SE to reorder (PR #77049)

[Brandon Wu via llvm-commits]

================
@@ -8832,72 +8901,117 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
         FixedIntrinsic->getMemoryVT(), FixedIntrinsic->getMemOperand());
   }
   case Intrinsic::riscv_sf_vc_x_se_e8mf8:
----------------
4vtomat wrote:

If we redefine `riscv_sf_vc_x_se*` to `riscv_sf_vc_x_se`, we should also change C intrinsics to match those IRs, but we are not able to distinguish between C intrinsics if we don't have suffix. We can make sew and luml as input operands in IR, but we can't add those to C intrinsics, can we?

https://github.com/llvm/llvm-project/pull/77049