[llvm] [X86] X86FixupVectorConstants - shrink vector load to movsd/movsd/movd/movq 'zero upper' instructions (PR #79000)

[Phoebe Wang via llvm-commits]

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@@ -50,7 +50,7 @@ define i32 @PR63108() {
 ; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm0 = [251,223,0,0,251,223,0,0,251,223,0,0,251,223,0,0]
 ; AVX1-NEXT:    jmp .LBB0_5
 ; AVX1-NEXT:  .LBB0_2: # %vector.body.preheader
-; AVX1-NEXT:    vmovaps {{.*#+}} xmm0 = [57339,0,0,0]
+; AVX1-NEXT:    vmovss {{.*#+}} xmm0 = [251,223,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
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phoebewang wrote:

I don't see FP domain instructions except for `vbroadcastss`, is it because they are using the same `xmm0` register?
Then I took a further look at `vbroadcastss`, and found maybe we should replace it with a `vmoss/vmod` too.

https://github.com/llvm/llvm-project/pull/79000