[llvm] a369619 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-01-23T11:30:06Z
New Revision: a3696196949ad03de2db266eea257d28d1f35905

URL: https://github.com/llvm/llvm-project/commit/a3696196949ad03de2db266eea257d28d1f35905
DIFF: https://github.com/llvm/llvm-project/commit/a3696196949ad03de2db266eea257d28d1f35905.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 52a9667b44104e0..874d10b979b801e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3141,7 +3141,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
         .setMIFlag(Flag);
     uint32_t PrevShiftAmount = 0;
     for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) {
-      if (NumOfVReg & (1 << ShiftAmount)) {
+      if (NumOfVReg & (1LL << ShiftAmount)) {
         if (ShiftAmount)
           BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
               .addReg(DestReg, RegState::Kill)