[llvm] [JITLink][AArch32] Implement Armv5 ldr-pc stubs and use them for all pre-v7 targets (PR #79082)

[Peter Smith via llvm-commits]

Stefan =?utf-8?q?Gränitz?= <stefan.graenitz at gmail.com>,
Stefan =?utf-8?q?Gränitz?= <stefan.graenitz at gmail.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/79082 at github.com>


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@@ -725,6 +725,60 @@ bool GOTBuilder::visitEdge(LinkGraph &G, Block *B, Edge &E) {
   return true;
 }
 
+/// Create a new node in the link-graph for the given stub template.
+template <size_t Size>
+static Block &allocStub(LinkGraph &G, Section &S, const uint8_t (&Code)[Size]) {
+  constexpr uint64_t Alignment = 4;
+  ArrayRef<char> Template(reinterpret_cast<const char *>(Code), Size);
+  return G.createContentBlock(S, Template, orc::ExecutorAddr(), Alignment, 0);
+}
+
+const uint8_t Armv5LongLdrPc[] = {
+    0x04, 0xf0, 0x1f, 0xe5, // ldr pc, [pc,#-4] ; L1
+    0x00, 0x00, 0x00, 0x00, // L1: .word S
+};
+
+    // TODO: There is only ARM far stub now. We should add the Thumb stub,
----------------
smithp35 wrote:

For future use:

Assuming JITLink can change a BL to a BLX then you can get away with just 2 stubs (or 4 if you want to support position independent stubs). The one you have above (Arm B and BL and Thumb BL via a BLX) and a Thumb one for Thumb B instructions. Usually for the Thumb stub it is a prefix that changes state to Arm. Something like:
```
// Thumb state entry
bx pc // branch over following 2-byte instruction due to pc-bias of 4
b #-6 // 2-byte branch instruction
// Arm state
ldr pr, [pc, #-4] ; L1
L1: .word S
```

https://github.com/llvm/llvm-project/pull/79082