[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> > > Do you have any performance or code size data to show that this change is a benefit to CPUs with RAS?
> > 
> > 
> > I don't have performance data as I don't have such hardware implementation. And I don't see code size change on llvm-test-suite. The thought of this PR came from a random discussion with my colleague, and ARM supports such feature. So I think maybe some low-end products need it.
> 
> It doesn't look like ARM uses it for register allocation though. This is the only code I can find on ARM that uses it
> 
> ```
>     if (!isDirect && !Subtarget->hasV5TOps())                                    
>       CallOpc = ARMISD::CALL_NOLINK;                                             
>     else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&           
>              // Emit regular call when code size is the priority                 
>              !Subtarget->hasMinSize())                                           
>       // "mov lr, pc; b _foo" to avoid confusing the RSP                         
>       CallOpc = ARMISD::CALL_NOLINK;                                             
>     else                                                                         
>       CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
> ```

This is some kind of reversion of your patch: https://reviews.llvm.org/D105875, it seems that we used to use GPR for JALR. The benefit is that such implementaion can have one more available register.
I don't have more data to support such configuration, so I'll let you guys decide whether we should support it. :-)

https://github.com/llvm/llvm-project/pull/78417