[llvm] cc2c8ab - Require asserts for llvm/test/CodeGen/PowerPC/sms-regpress.mir.

[Douglas Yung via llvm-commits]

Author: Douglas Yung
Date: 2024-01-22T13:51:03-08:00
New Revision: cc2c8ab21fd9b831799bff9ca99be2a2243d23b9

URL: https://github.com/llvm/llvm-project/commit/cc2c8ab21fd9b831799bff9ca99be2a2243d23b9
DIFF: https://github.com/llvm/llvm-project/commit/cc2c8ab21fd9b831799bff9ca99be2a2243d23b9.diff

LOG: Require asserts for llvm/test/CodeGen/PowerPC/sms-regpress.mir.

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/sms-regpress.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/sms-regpress.mir b/llvm/test/CodeGen/PowerPC/sms-regpress.mir
index f523b4548eecc9..cebd78af882dfd 100644
--- a/llvm/test/CodeGen/PowerPC/sms-regpress.mir
+++ b/llvm/test/CodeGen/PowerPC/sms-regpress.mir
@@ -1,5 +1,7 @@
 # RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner  -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s
 
+# REQUIRES: asserts
+
 # Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues.
 # The specific value of II is not important.