[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)

[Wang Pengcheng via llvm-commits]

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@@ -970,6 +970,9 @@ def FeatureFastUnalignedAccess
 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 
+def FeatureNoRAS : SubtargetFeature<"no-ras", "HasRAS", "false",
+                                    "Hasn't RAS (Return Address Stack)">;
+
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wangpc-pp wrote:

Yeah, RAS can be ambiguity as RAS can be `Reliability, Availability, Serviceability`.
I will align it to ARM later.

https://github.com/llvm/llvm-project/pull/78417