[llvm] 5ab2d9c - [RISCV] Arrange RISCVFeatures.td into sections of related extensions. NFC (#78790)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 22 00:04:50 PST 2024
Author: Craig Topper
Date: 2024-01-22T00:04:46-08:00
New Revision: 5ab2d9c0d9d4ea381cc2f5cbb047c1b1847d0b21
URL: https://github.com/llvm/llvm-project/commit/5ab2d9c0d9d4ea381cc2f5cbb047c1b1847d0b21
DIFF: https://github.com/llvm/llvm-project/commit/5ab2d9c0d9d4ea381cc2f5cbb047c1b1847d0b21.diff
LOG: [RISCV] Arrange RISCVFeatures.td into sections of related extensions. NFC (#78790)
Put I and Zi* together. Put F/D/Zf* together. Put A and Za* together,
etc.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 115da8c4a1a9357..cbb096ba20ae67b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -10,12 +10,7 @@
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
-def FeatureStdExtZicsr
- : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
- "'zicsr' (CSRs)">;
-def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
- AssemblerPredicate<(all_of FeatureStdExtZicsr),
- "'Zicsr' (CSRs)">;
+// Integer Extensions
def FeatureStdExtI
: SubtargetFeature<"i", "HasStdExtI", "true",
@@ -23,6 +18,115 @@ def FeatureStdExtI
def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">,
AssemblerPredicate<(all_of FeatureStdExtI),
"'I' (Base Integer Instruction Set)">;
+def FeatureStdExtZic64b
+ : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
+def FeatureStdExtZicbom
+ : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
+ "'Zicbom' (Cache-Block Management Instructions)">;
+def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicbom),
+ "'Zicbom' (Cache-Block Management Instructions)">;
+
+def FeatureStdExtZicbop
+ : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
+ "'Zicbop' (Cache-Block Prefetch Instructions)">;
+def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicbop),
+ "'Zicbop' (Cache-Block Prefetch Instructions)">;
+
+def FeatureStdExtZicboz
+ : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
+ "'Zicboz' (Cache-Block Zero Instructions)">;
+def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicboz),
+ "'Zicboz' (Cache-Block Zero Instructions)">;
+
+def FeatureStdExtZiccamoa
+ : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+ : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+ : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+ : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+
+def FeatureStdExtZicsr
+ : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+ "'zicsr' (CSRs)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicsr),
+ "'Zicsr' (CSRs)">;
+
+def FeatureStdExtZicntr
+ : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
+ "'Zicntr' (Base Counters and Timers)",
+ [FeatureStdExtZicsr]>;
+
+def FeatureStdExtZicond
+ : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
+ "'Zicond' (Integer Conditional Operations)">;
+def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicond),
+ "'Zicond' (Integer Conditional Operations)">;
+
+def FeatureStdExtZifencei
+ : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+ "'Zifencei' (fence.i)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+ AssemblerPredicate<(all_of FeatureStdExtZifencei),
+ "'Zifencei' (fence.i)">;
+
+def FeatureStdExtZihintpause
+ : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
+ "'Zihintpause' (Pause Hint)">;
+def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
+ AssemblerPredicate<(all_of FeatureStdExtZihintpause),
+ "'Zihintpause' (Pause Hint)">;
+
+def FeatureStdExtZihintntl
+ : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
+ "'Zihintntl' (Non-Temporal Locality Hints)">;
+def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
+ AssemblerPredicate<(all_of FeatureStdExtZihintntl),
+ "'Zihintntl' (Non-Temporal Locality Hints)">;
+
+def FeatureStdExtZihpm
+ : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
+ "'Zihpm' (Hardware Performance Counters)",
+ [FeatureStdExtZicsr]>;
+
+def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true",
+ "'Zimop' (May-Be-Operations)">;
+def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
+ AssemblerPredicate<(all_of FeatureStdExtZimop),
+ "'Zimop' (May-Be-Operations)">;
+
+def FeatureStdExtZicfilp
+ : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
+ "'Zicfilp' (Landing pad)">;
+def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicfilp),
+ "'Zicfilp' (Landing pad)">;
+
+def FeatureStdExtZicfiss
+ : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
+ "'Zicfiss' (Shadow stack)",
+ [FeatureStdExtZicsr, FeatureStdExtZimop]>;
+def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicfiss),
+ "'Zicfiss' (Shadow stack)">;
+def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+
+// Multiply Extensions
def FeatureStdExtM
: SubtargetFeature<"m", "HasStdExtM", "true",
@@ -41,6 +145,8 @@ def HasStdExtMOrZmmul
"'M' (Integer Multiplication and Division) or "
"'Zmmul' (Integer Multiplication)">;
+// Atomic Extensions
+
def FeatureStdExtA
: SubtargetFeature<"a", "HasStdExtA", "true",
"'A' (Atomic Instructions)">;
@@ -48,6 +154,36 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
+def FeatureStdExtZtso
+ : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
+ "'Ztso' (Memory Model - Total Store Order)">;
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
+ AssemblerPredicate<(all_of FeatureStdExtZtso),
+ "'Ztso' (Memory Model - Total Store Order)">;
+def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+
+def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+
+def FeatureStdExtZacas
+ : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
+ "'Zacas' (Atomic Compare-And-Swap Instructions)">;
+def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
+ AssemblerPredicate<(all_of FeatureStdExtZacas),
+ "'Zacas' (Atomic Compare-And-Swap Instructions)">;
+def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
+
+def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
+ "'Zawrs' (Wait on Reservation Set)">;
+def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
+ AssemblerPredicate<(all_of FeatureStdExtZawrs),
+ "'Zawrs' (Wait on Reservation Set)">;
+
+// Floating Point Extensions
+
def FeatureStdExtF
: SubtargetFeature<"f", "HasStdExtF", "true",
"'F' (Single-Precision Floating-Point)",
@@ -72,53 +208,6 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
AssemblerPredicate<(all_of FeatureStdExtH),
"'H' (Hypervisor)">;
-def FeatureStdExtZihintpause
- : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
- "'Zihintpause' (Pause Hint)">;
-def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
- AssemblerPredicate<(all_of FeatureStdExtZihintpause),
- "'Zihintpause' (Pause Hint)">;
-
-def FeatureStdExtZihintntl
- : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
- "'Zihintntl' (Non-Temporal Locality Hints)">;
-def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
- AssemblerPredicate<(all_of FeatureStdExtZihintntl),
- "'Zihintntl' (Non-Temporal Locality Hints)">;
-
-def FeatureStdExtZifencei
- : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
- "'Zifencei' (fence.i)">;
-def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
- AssemblerPredicate<(all_of FeatureStdExtZifencei),
- "'Zifencei' (fence.i)">;
-
-def FeatureStdExtZiccamoa
- : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
-
-def FeatureStdExtZiccif
- : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
-
-def FeatureStdExtZicclsm
- : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
-
-def FeatureStdExtZiccrse
- : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
-
-def FeatureStdExtZicntr
- : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
- "'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr]>;
-
-def FeatureStdExtZihpm
- : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
- "'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr]>;
-
def FeatureStdExtZfhmin
: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
@@ -136,12 +225,37 @@ def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
"'Zfh' (Half-Precision Floating-Point)">;
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
+// FIXME: Remove this.
def HasStdExtZfhOrZfhmin
: Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
+def FeatureStdExtZfbfmin
+ : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
+ "'Zfbfmin' (Scalar BF16 Converts)",
+ [FeatureStdExtF]>;
+def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
+ "'Zfbfmin' (Scalar BF16 Converts)">;
+
+def HasHalfFPLoadStoreMove
+ : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
+ AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
+ FeatureStdExtZfbfmin),
+ "'Zfh' (Half-Precision Floating-Point) or "
+ "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
+ "'Zfbfmin' (Scalar BF16 Converts)">;
+
+def FeatureStdExtZfa
+ : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
+ "'Zfa' (Additional Floating-Point)",
+ [FeatureStdExtF]>;
+def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfa),
+ "'Zfa' (Additional Floating-Point)">;
+
def FeatureStdExtZfinx
: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
"'Zfinx' (Float in Integer)",
@@ -181,13 +295,7 @@ def HasStdExtZhinxOrZhinxmin
"'Zhinx' (Half Float in Integer) or "
"'Zhinxmin' (Half Float in Integer Minimal)">;
-def FeatureStdExtZfa
- : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
- "'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>;
-def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
- AssemblerPredicate<(all_of FeatureStdExtZfa),
- "'Zfa' (Additional Floating-Point)">;
+// Compressed Extensions
def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true",
@@ -196,6 +304,88 @@ def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
+def FeatureNoRVCHints
+ : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
+ "Disable RVC Hint Instructions.">;
+def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
+ AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
+ "RVC Hint Instructions">;
+
+def FeatureStdExtZca
+ : SubtargetFeature<"zca", "HasStdExtZca", "true",
+ "'Zca' (part of the C extension, excluding compressed "
+ "floating point loads/stores)">;
+
+def HasStdExtCOrZca
+ : Predicate<"Subtarget->hasStdExtCOrZca()">,
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
+ "'C' (Compressed Instructions) or "
+ "'Zca' (part of the C extension, excluding "
+ "compressed floating point loads/stores)">;
+
+def FeatureStdExtZcb
+ : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
+ "'Zcb' (Compressed basic bit manipulation instructions)",
+ [FeatureStdExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZcb),
+ "'Zcb' (Compressed basic bit manipulation instructions)">;
+
+def FeatureStdExtZcd
+ : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
+ [FeatureStdExtZca]>;
+
+def HasStdExtCOrZcd
+ : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
+ "'C' (Compressed Instructions) or "
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+
+def FeatureStdExtZcf
+ : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
+ "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
+ [FeatureStdExtZca]>;
+
+def FeatureStdExtZcmp
+ : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
+ "'Zcmp' (sequenced instuctions for code-size reduction)",
+ [FeatureStdExtZca]>;
+def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
+ AssemblerPredicate<(all_of FeatureStdExtZcmp),
+ "'Zcmp' (sequenced instuctions for code-size reduction)">;
+
+def FeatureStdExtZcmt
+ : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
+ "'Zcmt' (table jump instuctions for code-size reduction)",
+ [FeatureStdExtZca, FeatureStdExtZicsr]>;
+def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
+ AssemblerPredicate<(all_of FeatureStdExtZcmt),
+ "'Zcmt' (table jump instuctions for code-size reduction)">;
+
+def FeatureStdExtZce
+ : SubtargetFeature<"zce", "HasStdExtZce", "true",
+ "'Zce' (Compressed extensions for microcontrollers)",
+ [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+ FeatureStdExtZcmt]>;
+
+def HasStdExtCOrZcfOrZce
+ : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
+ "Subtarget->hasStdExtZce()">,
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
+ FeatureStdExtZce),
+ "'C' (Compressed Instructions) or "
+ "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
+
+def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true",
+ "'Zcmop' (Compressed May-Be-Operations)",
+ [FeatureStdExtZca]>;
+def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
+ AssemblerPredicate<(all_of FeatureStdExtZcmop),
+ "'Zcmop' (Compressed May-Be-Operations)">;
+
+// Bitmanip Extensions
+
def FeatureStdExtZba
: SubtargetFeature<"zba", "HasStdExtZba", "true",
"'Zba' (Address Generation Instructions)">;
@@ -225,6 +415,8 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
+// Bitmanip Extensions for Cryptography Extensions
+
def FeatureStdExtZbkb
: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
"'Zbkb' (Bitmanip instructions for Cryptography)">;
@@ -264,6 +456,8 @@ def HasStdExtZbcOrZbkc
"'Zbkc' (Carry-less multiply instructions "
"for Cryptography)">;
+// Cryptography Extensions
+
def FeatureStdExtZknd
: SubtargetFeature<"zknd", "HasStdExtZknd", "true",
"'Zknd' (NIST Suite: AES Decryption)">;
@@ -345,78 +539,7 @@ def FeatureStdExtZk
FeatureStdExtZkr,
FeatureStdExtZkt]>;
-def FeatureStdExtZca
- : SubtargetFeature<"zca", "HasStdExtZca", "true",
- "'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)">;
-
-def HasStdExtCOrZca
- : Predicate<"Subtarget->hasStdExtCOrZca()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
- "'C' (Compressed Instructions) or "
- "'Zca' (part of the C extension, excluding "
- "compressed floating point loads/stores)">;
-
-def FeatureStdExtZcb
- : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
- "'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca]>;
-def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
- AssemblerPredicate<(all_of FeatureStdExtZcb),
- "'Zcb' (Compressed basic bit manipulation instructions)">;
-
-def FeatureStdExtZcd
- : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
- "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtZca]>;
-
-def HasStdExtCOrZcd
- : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
- "'C' (Compressed Instructions) or "
- "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
-
-def FeatureStdExtZcf
- : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
- "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtZca]>;
-
-def FeatureStdExtZcmp
- : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
- "'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca]>;
-def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
- AssemblerPredicate<(all_of FeatureStdExtZcmp),
- "'Zcmp' (sequenced instuctions for code-size reduction)">;
-
-def FeatureStdExtZcmt
- : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
- "'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr]>;
-def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
- AssemblerPredicate<(all_of FeatureStdExtZcmt),
- "'Zcmt' (table jump instuctions for code-size reduction)">;
-
-def FeatureStdExtZce
- : SubtargetFeature<"zce", "HasStdExtZce", "true",
- "'Zce' (Compressed extensions for microcontrollers)",
- [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
- FeatureStdExtZcmt]>;
-
-def HasStdExtCOrZcfOrZce
- : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
- "Subtarget->hasStdExtZce()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
- FeatureStdExtZce),
- "'C' (Compressed Instructions) or "
- "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-
-def FeatureNoRVCHints
- : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
- "Disable RVC Hint Instructions.">;
-def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
- AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
- "RVC Hint Instructions">;
+// Vector Extensions
def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
"'Zvl' (Minimum Vector Length) 32">;
@@ -464,34 +587,6 @@ def FeatureStdExtV
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
-def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
- AssemblerPredicate<
- (any_of FeatureStdExtZve32x),
- "'V' (Vector Extension for Application Processors), 'Zve32x' "
- "(Vector Extensions for Embedded Processors)">;
-def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
- AssemblerPredicate<
- (any_of FeatureStdExtZve64x),
- "'V' (Vector Extension for Application Processors) or 'Zve64x' "
- "(Vector Extensions for Embedded Processors)">;
-def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
- AssemblerPredicate<
- (any_of FeatureStdExtZve32f),
- "'V' (Vector Extension for Application Processors), 'Zve32f' "
- "(Vector Extensions for Embedded Processors)">;
-
-def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
-
-def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
-
-def FeatureStdExtZfbfmin
- : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
- "'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>;
-def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
- AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
- "'Zfbfmin' (Scalar BF16 Converts)">;
-
def FeatureStdExtZvfbfmin
: SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
"'Zvbfmin' (Vector BF16 Converts)",
@@ -508,8 +603,6 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
-def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
-
def FeatureStdExtZvfhmin
: SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
@@ -520,78 +613,13 @@ def FeatureStdExtZvfh
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
-def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
-
-def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
- AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
- "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
- "'Zvfh' (Vector Half-Precision Floating-Point)">;
-
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision Floating-Point)">;
-def FeatureStdExtZic64b
- : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
-
-def FeatureStdExtZicbom
- : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
- "'Zicbom' (Cache-Block Management Instructions)">;
-def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
- AssemblerPredicate<(all_of FeatureStdExtZicbom),
- "'Zicbom' (Cache-Block Management Instructions)">;
-
-def FeatureStdExtZicboz
- : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
- "'Zicboz' (Cache-Block Zero Instructions)">;
-def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
- AssemblerPredicate<(all_of FeatureStdExtZicboz),
- "'Zicboz' (Cache-Block Zero Instructions)">;
-
-def FeatureStdExtZicbop
- : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
-def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
- AssemblerPredicate<(all_of FeatureStdExtZicbop),
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
-
-def FeatureStdExtSvnapot
- : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
- "'Svnapot' (NAPOT Translation Contiguity)">;
-
-def FeatureStdExtSvpbmt
- : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
- "'Svpbmt' (Page-Based Memory Types)">;
-
-def FeatureStdExtSvinval
- : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
- "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
-def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
- AssemblerPredicate<(all_of FeatureStdExtSvinval),
- "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
-
-def FeatureStdExtZtso
- : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
- "'Ztso' (Memory Model - Total Store Order)">;
-def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
- AssemblerPredicate<(all_of FeatureStdExtZtso),
- "'Ztso' (Memory Model - Total Store Order)">;
-def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
-
-def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
-
-def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
-
-def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
- "'Zawrs' (Wait on Reservation Set)">;
-def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
- AssemblerPredicate<(all_of FeatureStdExtZawrs),
- "'Zawrs' (Wait on Reservation Set)">;
+// Vector Cryptography and Bitmanip Extensions
def FeatureStdExtZvkb
: SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
@@ -702,47 +730,41 @@ def FeatureStdExtZvksg
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
-def FeatureStdExtZicfilp
- : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
- "'Zicfilp' (Landing pad)">;
-def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
- AssemblerPredicate<(all_of FeatureStdExtZicfilp),
- "'Zicfilp' (Landing pad)">;
+// Vector instruction predicates
-def FeatureStdExtZicond
- : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
- "'Zicond' (Integer Conditional Operations)">;
-def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
- AssemblerPredicate<(all_of FeatureStdExtZicond),
- "'Zicond' (Integer Conditional Operations)">;
+def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
+ AssemblerPredicate<
+ (any_of FeatureStdExtZve32x),
+ "'V' (Vector Extension for Application Processors), 'Zve32x' "
+ "(Vector Extensions for Embedded Processors)">;
+def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
+ AssemblerPredicate<
+ (any_of FeatureStdExtZve64x),
+ "'V' (Vector Extension for Application Processors) or 'Zve64x' "
+ "(Vector Extensions for Embedded Processors)">;
+def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
+ AssemblerPredicate<
+ (any_of FeatureStdExtZve32f),
+ "'V' (Vector Extension for Application Processors), 'Zve32f' "
+ "(Vector Extensions for Embedded Processors)">;
-def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true",
- "'Zimop' (May-Be-Operations)">;
-def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
- AssemblerPredicate<(all_of FeatureStdExtZimop),
- "'Zimop' (May-Be-Operations)">;
+def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
+ "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
+ "'Zvfh' (Vector Half-Precision Floating-Point)">;
-def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true",
- "'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca]>;
-def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
- AssemblerPredicate<(all_of FeatureStdExtZcmop),
- "'Zcmop' (Compressed May-Be-Operations)">;
+def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
+def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
+def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
-def FeatureStdExtZicfiss
- : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
- "'Zicfiss' (Shadow stack)",
- [FeatureStdExtZicsr, FeatureStdExtZimop]>;
-def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
- AssemblerPredicate<(all_of FeatureStdExtZicfiss),
- "'Zicfiss' (Shadow stack)">;
-def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
+
+// Supervisor extensions
def FeatureStdExtSmaia
: SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
-
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
@@ -752,26 +774,27 @@ def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;
-def HasHalfFPLoadStoreMove
- : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
- AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
- FeatureStdExtZfbfmin),
- "'Zfh' (Half-Precision Floating-Point) or "
- "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
- "'Zfbfmin' (Scalar BF16 Converts)">;
+def FeatureStdExtSvinval
+ : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
+def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
+ AssemblerPredicate<(all_of FeatureStdExtSvinval),
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
-def FeatureStdExtZacas
- : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
- "'Zacas' (Atomic Compare-And-Swap Instructions)">;
-def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
- AssemblerPredicate<(all_of FeatureStdExtZacas),
- "'Zacas' (Atomic Compare-And-Swap Instructions)">;
-def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
+def FeatureStdExtSvnapot
+ : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+ "'Svnapot' (NAPOT Translation Contiguity)">;
+
+def FeatureStdExtSvpbmt
+ : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+ "'Svpbmt' (Page-Based Memory Types)">;
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
+// Ventana Extenions
+
def FeatureVendorXVentanaCondOps
: SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
"'XVentanaCondOps' (Ventana Conditional Ops)">;
@@ -779,6 +802,8 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()"
AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
"'XVentanaCondOps' (Ventana Conditional Ops)">;
+// T-Head Extensions
+
def FeatureVendorXTHeadBa
: SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
"'xtheadba' (T-Head address calculation instructions)">;
@@ -858,6 +883,8 @@ def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
"'xtheadvdot' (T-Head Vector Extensions for Dot)">;
+// SiFive Extensions
+
def FeatureVendorXSfvcp
: SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
@@ -897,6 +924,9 @@ def FeatureVendorXSfvfnrclipxfqf
def HasVendorXSfvfnrclipxfqf : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
+
+// Core-V Extensions
+
def FeatureVendorXCVelw
: SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
"'XCVelw' (CORE-V Event Load Word)">;
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