[llvm] [X86] Support encoding/decoding and lowering for APX variant SHL/SHR/SAR/SHLD/SHRD (PR #78853)

[Shengchen Kan via llvm-commits]

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@@ -180,10 +459,46 @@ multiclass Shlrd<bits<8> o1, bits<8> o2, string m, SDPatternOperator node, SDPat
   def 16mrCL : ShlrdOpMRC_M<o2, m, Xi16, t_node>, DefEFLAGS, OpSize16;
   def 32mrCL : ShlrdOpMRC_M<o2, m, Xi32, node>, DefEFLAGS, OpSize32;
   def 64mrCL : ShlrdOpMRC_M<o2, m, Xi64, node>, DefEFLAGS;
+
+  let Predicates = [HasNDD, In64BitMode] in {
+    def 16mri8_ND : ShlrdOpMRI8U_R<o3, m, Xi16, t_node>, DefEFLAGS, PD;
+    def 32mri8_ND : ShlrdOpMRI8U_R<o3, m, Xi32, node>, DefEFLAGS;
+    def 64mri8_ND : ShlrdOpMRI8U_R<o3, m, Xi64, node>, DefEFLAGS;
+
+    def 16mrCL_ND : ShlrdOpMRC_R<o2, m, Xi16, t_node>, DefEFLAGS, PD;
+    def 32mrCL_ND : ShlrdOpMRC_R<o2, m, Xi32, node>, DefEFLAGS;
+    def 64mrCL_ND : ShlrdOpMRC_R<o2, m, Xi64, node>, DefEFLAGS;
+  }
+
+  let Predicates = [In64BitMode] in {
+    def 16mri8_NF : ShlrdOpMRI8U_M<o3, m, Xi16, null_frag>, NF, PD;
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KanRobert wrote:

Done

https://github.com/llvm/llvm-project/pull/78853