[llvm] c2bef33 - [X86][NFC] Auto-generate the function to check predicate for EVEX compression

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-22T11:49:24+08:00
New Revision: c2bef33c5e61557314bbea6dcced710d18bcc413

URL: https://github.com/llvm/llvm-project/commit/c2bef33c5e61557314bbea6dcced710d18bcc413
DIFF: https://github.com/llvm/llvm-project/commit/c2bef33c5e61557314bbea6dcced710d18bcc413.diff

LOG: [X86][NFC] Auto-generate the function to check predicate for EVEX compression

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86CompressEVEX.cpp
    llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index a2bab9793b9cee..78a7e9850abdb2 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -121,44 +121,6 @@ static bool usesExtendedRegister(const MachineInstr &MI) {
   return false;
 }
 
-static bool checkVEXInstPredicate(unsigned OldOpc, const X86Subtarget &ST) {
-  switch (OldOpc) {
-  default:
-    return true;
-  case X86::VCVTNEPS2BF16Z128rm:
-  case X86::VCVTNEPS2BF16Z128rr:
-  case X86::VCVTNEPS2BF16Z256rm:
-  case X86::VCVTNEPS2BF16Z256rr:
-    return ST.hasAVXNECONVERT();
-  case X86::VPDPBUSDSZ128m:
-  case X86::VPDPBUSDSZ128r:
-  case X86::VPDPBUSDSZ256m:
-  case X86::VPDPBUSDSZ256r:
-  case X86::VPDPBUSDZ128m:
-  case X86::VPDPBUSDZ128r:
-  case X86::VPDPBUSDZ256m:
-  case X86::VPDPBUSDZ256r:
-  case X86::VPDPWSSDSZ128m:
-  case X86::VPDPWSSDSZ128r:
-  case X86::VPDPWSSDSZ256m:
-  case X86::VPDPWSSDSZ256r:
-  case X86::VPDPWSSDZ128m:
-  case X86::VPDPWSSDZ128r:
-  case X86::VPDPWSSDZ256m:
-  case X86::VPDPWSSDZ256r:
-    return ST.hasAVXVNNI();
-  case X86::VPMADD52HUQZ128m:
-  case X86::VPMADD52HUQZ128r:
-  case X86::VPMADD52HUQZ256m:
-  case X86::VPMADD52HUQZ256r:
-  case X86::VPMADD52LUQZ128m:
-  case X86::VPMADD52LUQZ128r:
-  case X86::VPMADD52LUQZ256m:
-  case X86::VPMADD52LUQZ256r:
-    return ST.hasAVXIFMA();
-  }
-}
-
 // Do any custom cleanup needed to finalize the conversion.
 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
   (void)NewOpc;
@@ -279,7 +241,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   }
 
   if (!IsND) {
-    if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) ||
+    if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) ||
         !performCustomAdjustments(MI, I->NewOpc))
       return false;
   }

diff  --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
index aa8527e75380c5..133eb9dfbf4bbc 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
@@ -46,8 +46,12 @@ class X86CompressEVEXTablesEmitter {
 
   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *>
       Entry;
+  typedef std::map<const Record *, std::vector<const CodeGenInstruction *>>
+      PredicateInstMap;
 
   std::vector<Entry> Table;
+  // Hold all compressed instructions that need to check predicate
+  PredicateInstMap PredicateInsts;
 
 public:
   X86CompressEVEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
@@ -58,12 +62,15 @@ class X86CompressEVEXTablesEmitter {
 private:
   // Prints the given table as a C++ array of type X86CompressEVEXTableEntry
   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
+  // Prints function which checks target feature for compressed instructions.
+  void printCheckPredicate(const PredicateInstMap &PredicateInsts,
+                           raw_ostream &OS);
 };
 
 void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
                                               raw_ostream &OS) {
 
-  OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = { \n";
+  OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = {\n";
 
   // Print all entries added to the table
   for (const auto &Pair : Table)
@@ -73,6 +80,22 @@ void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
   OS << "};\n\n";
 }
 
+void X86CompressEVEXTablesEmitter::printCheckPredicate(
+    const PredicateInstMap &PredicateInsts, raw_ostream &OS) {
+
+  OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget *Subtarget) {\n"
+     << "  switch (Opc) {\n"
+     << "  default: return true;\n";
+  for (const auto &[Key, Val] : PredicateInsts) {
+    for (const auto &Inst : Val)
+      OS << "  case X86::" << Inst->TheDef->getName() << ":\n";
+    OS << "    return " << Key->getValueAsString("CondString") << ";\n";
+  }
+
+  OS << "  }\n";
+  OS << "};\n\n";
+}
+
 static uint8_t byteFromBitsInit(const BitsInit *B) {
   unsigned N = B->getNumBits();
   assert(N <= 8 && "Field is too large for uint8_t!");
@@ -196,9 +219,18 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
       continue;
 
     Table.push_back(std::make_pair(Inst, NewInst));
+    auto Predicates = NewInst->TheDef->getValueAsListOfDefs("Predicates");
+    auto It = llvm::find_if(Predicates, [](const Record *R) {
+      StringRef Name = R->getName();
+      return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" ||
+             Name == "HasAVXIFMA";
+    });
+    if(It!= Predicates.end())
+      PredicateInsts[*It].push_back(NewInst);
   }
 
   printTable(Table, OS);
+  printCheckPredicate(PredicateInsts, OS);
 }
 } // namespace