[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[David Green via llvm-commits]

https://github.com/davemgreen approved this pull request.

Hi. I tried to give this a try on some Arm tests with it enabled, and seemed to it look OK. A few things got a little better and nothing seemed to break, which is a good sign.

I read through the code and it LGTM.

https://github.com/llvm/llvm-project/pull/74807