[llvm] [InstCombine] Resolve TODO: Remove one-time check if other logic operand (Y) is constant (PR #77973)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/77973

>From 1e6e96c6be0c025d64764c7a0bd5268d7b40fe2d Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Sun, 14 Jan 2024 12:53:37 -0500
Subject: [PATCH 1/2] [InstCombine] Add pre-commit tests [NFC]

---
 llvm/test/Transforms/InstCombine/shift-logic.ll | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/shift-logic.ll b/llvm/test/Transforms/InstCombine/shift-logic.ll
index 544694d398431e3..206a08a189d516a 100644
--- a/llvm/test/Transforms/InstCombine/shift-logic.ll
+++ b/llvm/test/Transforms/InstCombine/shift-logic.ll
@@ -16,6 +16,8 @@ define i8 @shl_and(i8 %x, i8 %y) {
   ret i8 %sh1
 }
 
+declare void @use1(<2 x i8>)
+
 define <2 x i8> @shl_and_nonuniform(<2 x i8> %x, <2 x i8> %y) {
 ; CHECK-LABEL: @shl_and_nonuniform(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 5, i8 4>
@@ -29,6 +31,21 @@ define <2 x i8> @shl_and_nonuniform(<2 x i8> %x, <2 x i8> %y) {
   ret <2 x i8> %sh1
 }
 
+define <2 x i8> @shl_and_nonuniform_multiuse(<2 x i8> %x) {
+; CHECK-LABEL: @shl_and_nonuniform_multiuse(
+; CHECK-NEXT:    [[SH0:%.*]] = shl <2 x i8> [[X:%.*]], <i8 3, i8 4>
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i8> [[SH0]], <i8 42, i8 42>
+; CHECK-NEXT:    call void @use1(<2 x i8> [[SH0]])
+; CHECK-NEXT:    [[SH1:%.*]] = shl nuw <2 x i8> [[R]], <i8 2, i8 0>
+; CHECK-NEXT:    ret <2 x i8> [[SH1]]
+;
+  %sh0 = shl <2 x i8> %x, <i8 3, i8 4>
+  %r = and <2 x i8> %sh0, <i8 42, i8 42> ; constant operand on the 'and'
+  call void @use1(<2 x i8> %sh0)
+  %sh1 = shl <2 x i8> %r, <i8 2, i8 0>
+  ret <2 x i8> %sh1
+}
+
 define i16 @shl_or(i16 %x, i16 %py) {
 ; CHECK-LABEL: @shl_or(
 ; CHECK-NEXT:    [[Y:%.*]] = srem i16 [[PY:%.*]], 42

>From d61544d06d0bca84fc876db031f11ba3108f10d1 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Fri, 12 Jan 2024 15:15:27 -0500
Subject: [PATCH 2/2] [Transforms] Remove one-time check if other logic operand
 (Y) is constant

By using match(W, m_ImmConstant()), we do not need to worry about one-time use anymore.
---
 .../InstCombine/InstCombineShifts.cpp           | 17 +++++++++--------
 llvm/test/Transforms/InstCombine/shift-logic.ll |  4 ++--
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index b7958978c450c98..b6f27295120db31 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -368,23 +368,24 @@ static Instruction *foldShiftOfShiftedBinOp(BinaryOperator &I,
 
   // Find a matching one-use shift by constant. The fold is not valid if the sum
   // of the shift values equals or exceeds bitwidth.
-  // TODO: Remove the one-use check if the other logic operand (Y) is constant.
   Value *X, *Y;
-  auto matchFirstShift = [&](Value *V) {
+  auto matchFirstShift = [&](Value *V, Value *W) {
     APInt Threshold(Ty->getScalarSizeInBits(), Ty->getScalarSizeInBits());
-    return match(V,
-                 m_OneUse(m_BinOp(ShiftOpcode, m_Value(X), m_Constant(C0)))) &&
-           match(ConstantExpr::getAdd(C0, C1),
-                 m_SpecificInt_ICMP(ICmpInst::ICMP_ULT, Threshold));
+    auto binOp = m_BinOp(ShiftOpcode, m_Value(X), m_Constant(C0));
+    return (match(W, m_ImmConstant()))
+               ? match(V, binOp)
+               : match(V, m_OneUse(binOp)) &&
+                     match(ConstantExpr::getAdd(C0, C1),
+                           m_SpecificInt_ICMP(ICmpInst::ICMP_ULT, Threshold));
   };
 
   // Logic ops and Add are commutative, so check each operand for a match. Sub
   // is not so we cannot reoder if we match operand(1) and need to keep the
   // operands in their original positions.
   bool FirstShiftIsOp1 = false;
-  if (matchFirstShift(BinInst->getOperand(0)))
+  if (matchFirstShift(BinInst->getOperand(0), BinInst->getOperand(1)))
     Y = BinInst->getOperand(1);
-  else if (matchFirstShift(BinInst->getOperand(1))) {
+  else if (matchFirstShift(BinInst->getOperand(1), BinInst->getOperand(0))) {
     Y = BinInst->getOperand(0);
     FirstShiftIsOp1 = BinInst->getOpcode() == Instruction::Sub;
   } else
diff --git a/llvm/test/Transforms/InstCombine/shift-logic.ll b/llvm/test/Transforms/InstCombine/shift-logic.ll
index 206a08a189d516a..a39fd49c67d3fda 100644
--- a/llvm/test/Transforms/InstCombine/shift-logic.ll
+++ b/llvm/test/Transforms/InstCombine/shift-logic.ll
@@ -34,9 +34,9 @@ define <2 x i8> @shl_and_nonuniform(<2 x i8> %x, <2 x i8> %y) {
 define <2 x i8> @shl_and_nonuniform_multiuse(<2 x i8> %x) {
 ; CHECK-LABEL: @shl_and_nonuniform_multiuse(
 ; CHECK-NEXT:    [[SH0:%.*]] = shl <2 x i8> [[X:%.*]], <i8 3, i8 4>
-; CHECK-NEXT:    [[R:%.*]] = and <2 x i8> [[SH0]], <i8 42, i8 42>
 ; CHECK-NEXT:    call void @use1(<2 x i8> [[SH0]])
-; CHECK-NEXT:    [[SH1:%.*]] = shl nuw <2 x i8> [[R]], <i8 2, i8 0>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i8> [[X]], <i8 5, i8 4>
+; CHECK-NEXT:    [[SH1:%.*]] = and <2 x i8> [[TMP1]], <i8 -88, i8 42>
 ; CHECK-NEXT:    ret <2 x i8> [[SH1]]
 ;
   %sh0 = shl <2 x i8> %x, <i8 3, i8 4>