[llvm] [X86][APX]Support lowering for APX promoted AMX-TILE instructions (PR #78689)

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git-clang-format --diff 595d780b492d3de3f5653851e7d64c122472d71a fb5a25660a839473b16d9c7d27d11fcb87d0bcdc -- llvm/lib/Target/X86/X86ExpandPseudo.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86LowerTileCopy.cpp
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 78bc14c977..974b6a176f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36375,9 +36375,15 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     switch (MI.getOpcode()) {
     default: llvm_unreachable("illegal opcode!");
 #define GET_EGPR_IF_ENABLED(OPC) (Subtarget.hasEGPR() ? OPC##_EVEX : OPC)
-    case X86::PTILELOADD:   Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD);   break;
-    case X86::PTILELOADDT1: Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1); break;
-    case X86::PTILESTORED:  Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED);  break;
+    case X86::PTILELOADD:
+      Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD);
+      break;
+    case X86::PTILELOADDT1:
+      Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1);
+      break;
+    case X86::PTILESTORED:
+      Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED);
+      break;
 #undef GET_EGPR_IF_ENABLED
     }
 

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https://github.com/llvm/llvm-project/pull/78689