[llvm] [HEXAGON] Inlining Division (PR #78674)
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Thu Jan 18 22:14:23 PST 2024
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
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git-clang-format --diff 15c1c85470a17283bd86fe68a702c74599bdcb5c 9234117e84979e3515ebf1f88a973316589fe088 -- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h llvm/lib/Target/Hexagon/HexagonISelLowering.cpp llvm/lib/Target/Hexagon/HexagonISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 56d35e5875..6fe3fe0d36 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1041,7 +1041,8 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
case HexagonISD::D2P: return SelectD2P(N);
case HexagonISD::Q2V: return SelectQ2V(N);
case HexagonISD::V2Q: return SelectV2Q(N);
- case ISD::FDIV: return SelectFDiv(N);
+ case ISD::FDIV:
+ return SelectFDiv(N);
}
SelectCode(N);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 6a07cacc31..13691053dd 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -653,8 +653,7 @@ bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
}
-SDValue
-HexagonTargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
+SDValue HexagonTargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
if (DAG.getMachineFunction().getFunction().hasOptSize())
return SDValue();
else
@@ -3351,7 +3350,8 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
#endif
llvm_unreachable("Should not custom lower this!");
- case ISD::FDIV: return LowerFDIV(Op, DAG);
+ case ISD::FDIV:
+ return LowerFDIV(Op, DAG);
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
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https://github.com/llvm/llvm-project/pull/78674
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