[llvm] [RISCV] Fix stack size computation when M extension disabled (PR #78602)

[Alex Bradbury via llvm-commits]

asb wrote:

@simeonkr do you have a core where this is needed? Although the RISC-V ISA allows vector extensions without M, I'm wondering if that case is worth supporting in LLVM.

> @asb I surmise there may be certain embedded RV32I cores out there that might require it, but we don't have any on our end. However, the code in question was the only place I found where we emit a mul instruction, so I don't anticipate much effort beyond this patch to support this configuration.

Sounds good. If we reasonably expect this is the only place that needs fixing then it seems perfectly sensible to support.

https://github.com/llvm/llvm-project/pull/78602