[llvm] [RISCV][ISel] Add ISel support for experimental Zimop extension (PR #77089)

[Jivan Hakobyan via llvm-commits]

================
@@ -8404,6 +8404,83 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
         IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
     return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
   }
+  case Intrinsic::riscv_mopr: {
+    unsigned mopr_id = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+    switch (mopr_id) {
+#define RISCV_MOPR_64_CASE(MOPR_ID, OPCODE)                                    \
+  case MOPR_ID: {                                                              \
+    if (RV64LegalI32 && Subtarget.is64Bit() &&                                 \
+        Op.getValueType() == MVT::i32) {                                       \
+      SDValue NewOp =                                                          \
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));        \
+      SDValue Res = DAG.getNode(OPCODE, DL, MVT::i64, NewOp);                  \
+      return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);                    \
+    }                                                                          \
+    return DAG.getNode(OPCODE, DL, XLenVT, Op.getOperand(1));                  \
+  }
+      RISCV_MOPR_64_CASE(0, RISCVISD::MOPR0)
----------------
JivanH wrote:

I guess @ln8-8 tried to append the third argument to the instruction name and avoid defining 8/32 patterns for mapr/moprr instructions. 
Did something like this

```
def : Pat<(XLenVT (riscv_mopr GPR:$rs1, uimm5:$imm)),
            (!cast<Instruction>("MOPR"#!repr($imm->getSExtValue())) GPR:$rs1)>;
```

Anyway, Thank you.

https://github.com/llvm/llvm-project/pull/77089