[llvm] [RISCV] Fix stack size computation when M extension disabled (PR #78602)
Simeon K via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 08:04:41 PST 2024
https://github.com/simeonkr created https://github.com/llvm/llvm-project/pull/78602
Ensure that getVLENFactoredAmount does not fail when the scale amount requires the use of a non-trivial multiplication but the M extension is not enabled. In such case, perform the multiplication using shifts and adds.
>From 1cd98a36778fe9a07a5f2a1d4326126d6e82e544 Mon Sep 17 00:00:00 2001
From: Simeon Krastnikov <simeon.krastnikov at imgtec.com>
Date: Thu, 18 Jan 2024 15:54:06 +0000
Subject: [PATCH] [RISCV] Fix stack size computation when M extension disabled
Ensure that getVLENFactoredAmount does not fail when the scale amount
requires the use of a non-trivial multiplication but the M extension is
not enabled. In such case, perform the multiplication using shifts and
adds.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 33 ++++++++--
.../CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll | 62 +++++++++++++++++++
2 files changed, 89 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 857e8979762cdc..c3ebf6ce83e3f1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3159,18 +3159,39 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
.addReg(ScaledRegister, RegState::Kill)
.addReg(DestReg, RegState::Kill)
.setMIFlag(Flag);
- } else {
+ } else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) {
Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
movImm(MBB, II, DL, N, NumOfVReg, Flag);
- if (!STI.hasStdExtM() && !STI.hasStdExtZmmul())
- MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
- MF.getFunction(),
- "M- or Zmmul-extension must be enabled to calculate the vscaled size/"
- "offset."});
BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg)
.addReg(DestReg, RegState::Kill)
.addReg(N, RegState::Kill)
.setMIFlag(Flag);
+ } else {
+ Register Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ BuildMI(MBB, II, DL, get(RISCV::ADDI), Acc)
+ .addReg(RISCV::X0)
+ .addImm(0)
+ .setMIFlag(Flag);
+ uint32_t PrevShiftAmount = 0;
+ for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) {
+ if (NumOfVReg & (1 << ShiftAmount)) {
+ if (ShiftAmount)
+ BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
+ .addReg(DestReg, RegState::Kill)
+ .addImm(ShiftAmount - PrevShiftAmount)
+ .setMIFlag(Flag);
+ if (NumOfVReg >> (ShiftAmount + 1))
+ BuildMI(MBB, II, DL, get(RISCV::ADD), Acc)
+ .addReg(Acc, RegState::Kill)
+ .addReg(DestReg)
+ .setMIFlag(Flag);
+ PrevShiftAmount = ShiftAmount;
+ }
+ }
+ BuildMI(MBB, II, DL, get(RISCV::ADD), DestReg)
+ .addReg(DestReg, RegState::Kill)
+ .addReg(Acc)
+ .setMIFlag(Flag);
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
index e6adb725110a40..78bec6c68c3f6e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -3,6 +3,8 @@
; RUN: | FileCheck %s --check-prefixes=CHECK,NOZBA
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZBA
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,NOMUL
define void @lmul1() nounwind {
; CHECK-LABEL: lmul1:
@@ -243,6 +245,26 @@ define void @lmul4_and_2_x2_1() nounwind {
; ZBA-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; ZBA-NEXT: addi sp, sp, 48
; ZBA-NEXT: ret
+;
+; NOMUL-LABEL: lmul4_and_2_x2_1:
+; NOMUL: # %bb.0:
+; NOMUL-NEXT: addi sp, sp, -48
+; NOMUL-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: addi s0, sp, 48
+; NOMUL-NEXT: csrr a0, vlenb
+; NOMUL-NEXT: li a1, 0
+; NOMUL-NEXT: slli a0, a0, 2
+; NOMUL-NEXT: add a1, a1, a0
+; NOMUL-NEXT: slli a0, a0, 1
+; NOMUL-NEXT: add a0, a0, a1
+; NOMUL-NEXT: sub sp, sp, a0
+; NOMUL-NEXT: andi sp, sp, -32
+; NOMUL-NEXT: addi sp, s0, -48
+; NOMUL-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: addi sp, sp, 48
+; NOMUL-NEXT: ret
%v1 = alloca <vscale x 4 x i64>
%v3 = alloca <vscale x 4 x i64>
%v2 = alloca <vscale x 2 x i64>
@@ -425,6 +447,26 @@ define void @lmul_8_x5() nounwind {
; ZBA-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZBA-NEXT: addi sp, sp, 80
; ZBA-NEXT: ret
+;
+; NOMUL-LABEL: lmul_8_x5:
+; NOMUL: # %bb.0:
+; NOMUL-NEXT: addi sp, sp, -80
+; NOMUL-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: addi s0, sp, 80
+; NOMUL-NEXT: csrr a0, vlenb
+; NOMUL-NEXT: li a1, 0
+; NOMUL-NEXT: slli a0, a0, 3
+; NOMUL-NEXT: add a1, a1, a0
+; NOMUL-NEXT: slli a0, a0, 2
+; NOMUL-NEXT: add a0, a0, a1
+; NOMUL-NEXT: sub sp, sp, a0
+; NOMUL-NEXT: andi sp, sp, -64
+; NOMUL-NEXT: addi sp, s0, -80
+; NOMUL-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: addi sp, sp, 80
+; NOMUL-NEXT: ret
%v1 = alloca <vscale x 8 x i64>
%v2 = alloca <vscale x 8 x i64>
%v3 = alloca <vscale x 8 x i64>
@@ -467,6 +509,26 @@ define void @lmul_8_x9() nounwind {
; ZBA-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZBA-NEXT: addi sp, sp, 80
; ZBA-NEXT: ret
+;
+; NOMUL-LABEL: lmul_8_x9:
+; NOMUL: # %bb.0:
+; NOMUL-NEXT: addi sp, sp, -80
+; NOMUL-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; NOMUL-NEXT: addi s0, sp, 80
+; NOMUL-NEXT: csrr a0, vlenb
+; NOMUL-NEXT: li a1, 0
+; NOMUL-NEXT: slli a0, a0, 3
+; NOMUL-NEXT: add a1, a1, a0
+; NOMUL-NEXT: slli a0, a0, 3
+; NOMUL-NEXT: add a0, a0, a1
+; NOMUL-NEXT: sub sp, sp, a0
+; NOMUL-NEXT: andi sp, sp, -64
+; NOMUL-NEXT: addi sp, s0, -80
+; NOMUL-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; NOMUL-NEXT: addi sp, sp, 80
+; NOMUL-NEXT: ret
%v1 = alloca <vscale x 8 x i64>
%v2 = alloca <vscale x 8 x i64>
%v3 = alloca <vscale x 8 x i64>
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