[llvm] d12dffa - [X86] Add X86::getConstantFromPool helper function to replace duplicate implementations.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 04:02:02 PST 2024
Author: Simon Pilgrim
Date: 2024-01-18T11:59:46Z
New Revision: d12dffacaa838cbdd30454e49214f40d2ec1cc50
URL: https://github.com/llvm/llvm-project/commit/d12dffacaa838cbdd30454e49214f40d2ec1cc50
DIFF: https://github.com/llvm/llvm-project/commit/d12dffacaa838cbdd30454e49214f40d2ec1cc50.diff
LOG: [X86] Add X86::getConstantFromPool helper function to replace duplicate implementations.
We had the same helper function in shuffle decode / vector constant code - move this to X86InstrInfo to avoid duplication.
Added:
Modified:
llvm/lib/Target/X86/X86FixupVectorConstants.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
llvm/lib/Target/X86/X86MCInstLower.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 483becebbe1066..8fcf0779064938 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -63,23 +63,6 @@ FunctionPass *llvm::createX86FixupVectorConstants() {
return new X86FixupVectorConstantsPass();
}
-static const Constant *getConstantFromPool(const MachineInstr &MI,
- const MachineOperand &Op) {
- if (!Op.isCPI() || Op.getOffset() != 0)
- return nullptr;
-
- ArrayRef<MachineConstantPoolEntry> Constants =
- MI.getParent()->getParent()->getConstantPool()->getConstants();
- const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
-
- // Bail if this is a machine constant pool entry, we won't be able to dig out
- // anything useful.
- if (ConstantEntry.isMachineConstantPoolEntry())
- return nullptr;
-
- return ConstantEntry.Val.ConstVal;
-}
-
// Attempt to extract the full width of bits data from the constant.
static std::optional<APInt> extractConstantBits(const Constant *C) {
unsigned NumBits = C->getType()->getPrimitiveSizeInBits();
@@ -244,7 +227,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
"Unexpected number of operands!");
MachineOperand &CstOp = MI.getOperand(OperandNo + X86::AddrDisp);
- if (auto *C = getConstantFromPool(MI, CstOp)) {
+ if (auto *C = X86::getConstantFromPool(MI, CstOp)) {
// Attempt to detect a suitable splat from increasing splat widths.
std::pair<unsigned, unsigned> Broadcasts[] = {
{8, OpBcst8}, {16, OpBcst16}, {32, OpBcst32},
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 907b3cd69591f6..8b454a2cde4160 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3514,6 +3514,23 @@ int X86::getFirstAddrOperandIdx(const MachineInstr &MI) {
return -1;
}
+const Constant *X86::getConstantFromPool(const MachineInstr &MI,
+ const MachineOperand &Op) {
+ if (!Op.isCPI() || Op.getOffset() != 0)
+ return nullptr;
+
+ ArrayRef<MachineConstantPoolEntry> Constants =
+ MI.getParent()->getParent()->getConstantPool()->getConstants();
+ const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
+
+ // Bail if this is a machine constant pool entry, we won't be able to dig out
+ // anything useful.
+ if (ConstantEntry.isMachineConstantPoolEntry())
+ return nullptr;
+
+ return ConstantEntry.Val.ConstVal;
+}
+
bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
case X86::TCRETURNdi:
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 622081054abd7a..407bb87267408c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -86,6 +86,10 @@ bool isX87Instruction(MachineInstr &MI);
/// real instructions (e.g., JMP64m).
int getFirstAddrOperandIdx(const MachineInstr &MI);
+/// Find any constant pool entry associated with a specific instruction operand.
+const Constant *getConstantFromPool(const MachineInstr &MI,
+ const MachineOperand &Op);
+
} // namespace X86
/// isGlobalStubReference - Return true if the specified TargetFlag operand is
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 5aad99c74eb614..fc9e748157192d 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1399,23 +1399,6 @@ PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
return MBBI;
}
-static const Constant *getConstantFromPool(const MachineInstr &MI,
- const MachineOperand &Op) {
- if (!Op.isCPI() || Op.getOffset() != 0)
- return nullptr;
-
- ArrayRef<MachineConstantPoolEntry> Constants =
- MI.getParent()->getParent()->getConstantPool()->getConstants();
- const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
-
- // Bail if this is a machine constant pool entry, we won't be able to dig out
- // anything useful.
- if (ConstantEntry.isMachineConstantPoolEntry())
- return nullptr;
-
- return ConstantEntry.Val.ConstVal;
-}
-
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
unsigned SrcOp2Idx, ArrayRef<int> Mask) {
std::string Comment;
@@ -1674,7 +1657,7 @@ static void addConstantComments(const MachineInstr *MI,
"Unexpected number of operands!");
const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
- if (auto *C = getConstantFromPool(*MI, MaskOp)) {
+ if (auto *C = X86::getConstantFromPool(*MI, MaskOp)) {
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
SmallVector<int, 64> Mask;
DecodePSHUFBMask(C, Width, Mask);
@@ -1752,7 +1735,7 @@ static void addConstantComments(const MachineInstr *MI,
"Unexpected number of operands!");
const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
- if (auto *C = getConstantFromPool(*MI, MaskOp)) {
+ if (auto *C = X86::getConstantFromPool(*MI, MaskOp)) {
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
SmallVector<int, 16> Mask;
DecodeVPERMILPMask(C, ElSize, Width, Mask);
@@ -1781,7 +1764,7 @@ static void addConstantComments(const MachineInstr *MI,
}
const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp);
- if (auto *C = getConstantFromPool(*MI, MaskOp)) {
+ if (auto *C = X86::getConstantFromPool(*MI, MaskOp)) {
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
SmallVector<int, 16> Mask;
DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
@@ -1796,7 +1779,7 @@ static void addConstantComments(const MachineInstr *MI,
"Unexpected number of operands!");
const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp);
- if (auto *C = getConstantFromPool(*MI, MaskOp)) {
+ if (auto *C = X86::getConstantFromPool(*MI, MaskOp)) {
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
SmallVector<int, 16> Mask;
DecodeVPPERMMask(C, Width, Mask);
@@ -1809,7 +1792,8 @@ static void addConstantComments(const MachineInstr *MI,
case X86::MMX_MOVQ64rm: {
assert(MI->getNumOperands() == (1 + X86::AddrNumOperands) &&
"Unexpected number of operands!");
- if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
+ if (auto *C =
+ X86::getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
std::string Comment;
raw_string_ostream CS(Comment);
const MachineOperand &DstOp = MI->getOperand(0);
@@ -1881,7 +1865,8 @@ static void addConstantComments(const MachineInstr *MI,
case X86::VBROADCASTI64X4rm:
assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) &&
"Unexpected number of operands!");
- if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
+ if (auto *C =
+ X86::getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
int NumLanes = 1;
int BitWidth = 128;
int CstEltSize = C->getType()->getScalarSizeInBits();
@@ -1984,7 +1969,8 @@ static void addConstantComments(const MachineInstr *MI,
case X86::VPBROADCASTWZrm:
assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) &&
"Unexpected number of operands!");
- if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
+ if (auto *C =
+ X86::getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
int NumElts, EltBits;
switch (MI->getOpcode()) {
default: llvm_unreachable("Invalid opcode");
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