[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 01:52:01 PST 2024
BeMg wrote:
These testcases from LLVM lit generate the worse assembly after applying the postRA VSETVL insertion pass.
Most of them are affected by the scheduler and allocator. Cause the extra move instruction and spill/reload code.
Based on STATISTIC inside LLVM, they could be categorized as the testcases for extra spill/reload and extra VSETVL instruction.
## Extra SPILL/RELOAD
| TEST |Extra SPILL|Extra RELOAD|
|-----------------------------------|-----------|------------|
|fixed-vectors-cttz-vp.ll |14 |30 |
|fixed-vectors-ctlz-vp.ll |14 |30 |
|fixed-vectors-ctpop-vp.ll |7 |13 |
|fixed-vectors-interleaved-access.ll|5 |3 |
|vselect-vp.ll |4 |4 |
|vfnmadd-constrained-sdnode.ll |2 |3 |
|vfmadd-sdnode.ll |2 |2 |
|bswap-vp.ll |2 |2 |
|bitreverse-vp.ll |2 |2 |
|fixed-vectors-bitreverse-vp.ll |2 |2 |
|vfmsub-constrained-sdnode.ll |2 |2 |
|fixed-vectors-vselect-vp.ll |2 |2 |
|fixed-vectors-bswap-vp.ll |2 |2 |
|vfnmsub-constrained-sdnode.ll |1 |1 |
|fixed-vectors-vcopysign-vp.ll |1 |1 |
|fixed-vectors-vfmax-vp.ll |1 |1 |
|fixed-vectors-vfmin-vp.ll |1 |1 |
|fixed-vectors-trunc-vp.ll |1 |1 |
|vector-deinterleave-load.ll |1 |1 |
|vector-deinterleave.ll |1 |1 |
|vsitofp-vp.ll |1 |1 |
|vuitofp-vp.ll |1 |1 |
|vfptosi-vp.ll |1 |1 |
|vfptoui-vp.ll |1 |1 |
|ctpop-vp.ll |1 |0 |
## Extra VSETVL
| TEST |Extra VSETVL|
|------------------------------------------|------------|
|fixed-vectors-fp2i.ll |4 |
|fixed-vectors-interleaved-access-zve32x.ll|4 |
|fixed-vectors-interleaved-access.ll |3 |
|fixed-vectors-vand-vp.ll |2 |
|fixed-vectors-int-explodevector.ll |2 |
|fixed-vectors-rint-vp.ll |2 |
|fixed-vectors-insert-subvector.ll |1 |
|fixed-vectors-vselect-vp.ll |1 |
|fixed-vectors-buildvec-of-binop.ll |1 |
https://github.com/llvm/llvm-project/pull/70549
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