[llvm] Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack (PR #78553)
Rajveer Singh Bharadwaj via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 01:11:52 PST 2024
https://github.com/Rajveer100 created https://github.com/llvm/llvm-project/pull/78553
Resolves Issue #78226
Update the argument list for `*_Gfx` calling conventions for AMDGPU calling convention and update the conditional check under `enableFlatScratch` which pre-allocates the registers.
>From 4f341fed19f2e88eb19deab5f7fef3acfdd69294 Mon Sep 17 00:00:00 2001
From: Rajveer <rajveer.developer at icloud.com>
Date: Thu, 18 Jan 2024 14:33:19 +0530
Subject: [PATCH] Update amdgpu_gfx functions to use s0-s3 for inreg SGPR
arguments on targets using scratch instructions for stack
Resolves Issue #78226
---
llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 1 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index c5207228dc913fe..4c922a81c02efd5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -23,6 +23,7 @@ def CC_SI_Gfx : CallingConv<[
// 33 is reserved for the frame pointer
// 34 is reserved for the base pointer
CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
+ SGPR0, SGPR1, SGPR2, SGPR3,
SGPR4, SGPR5, SGPR6, SGPR7,
SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3852f93da98dc45..2a5cd441d6e215f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2786,7 +2786,7 @@ SDValue SITargetLowering::LowerFormalArguments(
if (!IsKernel) {
CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
- if (!IsGraphics && !Subtarget->enableFlatScratch()) {
+ if (!Subtarget->enableFlatScratch()) {
CCInfo.AllocateRegBlock(ArrayRef<MCPhysReg>{AMDGPU::SGPR0, AMDGPU::SGPR1,
AMDGPU::SGPR2, AMDGPU::SGPR3},
4);
More information about the llvm-commits
mailing list