[llvm] [Xtensa] Initial support of the ALU operations and ConstantPool (PR #78548)
Andrei Safronov via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 23:50:44 PST 2024
https://github.com/andreisfr created https://github.com/llvm/llvm-project/pull/78548
This PR provides implementation of the basic codegen infra such as TargetFrameLowering, CallingConv, TargetLowering, SelectionDAGISe. Initial ConstantPool support has also been implemented.
The PR contains five commits that were originally published on Phabricator (third patch is approved), each commit depends on previous commits, and together these patches provide support for more complex IR tests. Patches have been updated based on reviewers comments from Phabricator and slightly refactored.
Migrated from:
https://reviews.llvm.org/D145658
https://reviews.llvm.org/D145660
https://reviews.llvm.org/D145661 (this Differential is approved in Phabricator)
https://reviews.llvm.org/D145662
https://reviews.llvm.org/D145663
>From 5fcc08eacc0ace88abf26c61f62bf54755253e66 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Wed, 26 Jul 2023 00:34:01 +0300
Subject: [PATCH 1/5] [Xtensa] Initial support of the ALU operations.
Initial codegen support for simple ALU operations. Added basic
implementation of the TargetFrameLowering, CallingConv,
TargetLowering, SelectionDAGISel etc.
---
llvm/lib/Target/Xtensa/CMakeLists.txt | 11 +
.../Xtensa/MCTargetDesc/XtensaAsmBackend.cpp | 2 +-
.../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 8 +-
.../MCTargetDesc/XtensaMCCodeEmitter.cpp | 6 +-
.../Xtensa/MCTargetDesc/XtensaMCExpr.cpp | 2 +-
llvm/lib/Target/Xtensa/Xtensa.h | 30 ++
llvm/lib/Target/Xtensa/Xtensa.td | 6 +
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 41 +++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 42 +++
llvm/lib/Target/Xtensa/XtensaCallingConv.td | 30 ++
.../lib/Target/Xtensa/XtensaFrameLowering.cpp | 44 +++
llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 34 ++
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 81 +++++
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 330 ++++++++++++++++++
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 64 ++++
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 27 ++
llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 43 +++
llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 8 +-
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 62 ++++
llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 43 +++
llvm/lib/Target/Xtensa/XtensaOperators.td | 15 +
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 70 ++++
llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 56 +++
llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 46 +++
llvm/lib/Target/Xtensa/XtensaSubtarget.h | 72 ++++
.../lib/Target/Xtensa/XtensaTargetMachine.cpp | 30 +-
llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 6 +
llvm/test/CodeGen/Xtensa/alu.ll | 158 +++++++++
28 files changed, 1355 insertions(+), 12 deletions(-)
create mode 100644 llvm/lib/Target/Xtensa/Xtensa.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaCallingConv.td
create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaOperators.td
create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.h
create mode 100644 llvm/test/CodeGen/Xtensa/alu.ll
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 7192f7392072b31..bb1e09cb0652ecf 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -4,6 +4,8 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv)
+tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
@@ -13,6 +15,14 @@ tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XtensaCommonTableGen)
add_llvm_target(XtensaCodeGen
+ XtensaAsmPrinter.cpp
+ XtensaFrameLowering.cpp
+ XtensaInstrInfo.cpp
+ XtensaISelDAGToDAG.cpp
+ XtensaISelLowering.cpp
+ XtensaMCInstLower.cpp
+ XtensaRegisterInfo.cpp
+ XtensaSubtarget.cpp
XtensaTargetMachine.cpp
LINK_COMPONENTS
@@ -20,6 +30,7 @@ add_llvm_target(XtensaCodeGen
CodeGen
Core
MC
+ SelectionDAG
Support
Target
XtensaDesc
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
index db4484bb57c1ad7..c87e2187b73d4e6 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
@@ -84,7 +84,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
unsigned Kind = Fixup.getKind();
switch (Kind) {
default:
- llvm_unreachable("Unknown fixup kind!");
+ report_fatal_error("Unknown fixup kind!");
case FK_Data_1:
case FK_Data_2:
case FK_Data_4:
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
index fe1dc0e2e483e72..f234d5e900a472a 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -102,7 +102,7 @@ void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum,
} else if (MC.isExpr())
MC.getExpr()->print(OS, &MAI, true);
else
- llvm_unreachable("Invalid operand");
+ report_fatal_error("Invalid operand");
}
void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum,
@@ -117,7 +117,7 @@ void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum,
} else if (MC.isExpr())
MC.getExpr()->print(OS, &MAI, true);
else
- llvm_unreachable("Invalid operand");
+ report_fatal_error("Invalid operand");
;
}
@@ -133,7 +133,7 @@ void XtensaInstPrinter::printCallOperand(const MCInst *MI, int OpNum,
} else if (MC.isExpr())
MC.getExpr()->print(OS, &MAI, true);
else
- llvm_unreachable("Invalid operand");
+ report_fatal_error("Invalid operand");
}
void XtensaInstPrinter::printL32RTarget(const MCInst *MI, int OpNum,
@@ -151,7 +151,7 @@ void XtensaInstPrinter::printL32RTarget(const MCInst *MI, int OpNum,
} else if (MC.isExpr())
MC.getExpr()->print(O, &MAI, true);
else
- llvm_unreachable("Invalid operand");
+ report_fatal_error("Invalid operand");
}
void XtensaInstPrinter::printImm8_AsmOperand(const MCInst *MI, int OpNum,
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
index 1afdbb38f9571a2..c6941499cba192d 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -203,7 +203,7 @@ XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum,
if (MO.isImm()) {
int32_t Res = MO.getImm();
if (Res & 0x3) {
- llvm_unreachable("Unexpected operand value!");
+ report_fatal_error("Unexpected operand value!");
}
Res >>= 2;
return Res;
@@ -396,7 +396,7 @@ XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,
Res = 15;
break;
default:
- llvm_unreachable("Unexpected operand value!");
+ report_fatal_error("Unexpected operand value!");
}
return Res;
@@ -446,7 +446,7 @@ XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,
Res = 15;
break;
default:
- llvm_unreachable("Unexpected operand value!");
+ report_fatal_error("Unexpected operand value!");
}
return Res;
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
index cafd8b7e2978202..2d0db1aae0645b3 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
@@ -58,6 +58,6 @@ XtensaMCExpr::VariantKind XtensaMCExpr::getVariantKindForName(StringRef name) {
StringRef XtensaMCExpr::getVariantKindName(VariantKind Kind) {
switch (Kind) {
default:
- llvm_unreachable("Invalid ELF symbol kind");
+ report_fatal_error("Invalid ELF symbol kind");
}
}
diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h
new file mode 100644
index 000000000000000..1d6e2a2b32f1526
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Xtensa.h
@@ -0,0 +1,30 @@
+//===- Xtensa.h - Top-level interface for Xtensa representation -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in
+// the LLVM Xtensa back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSA_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSA_H
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/PassRegistry.h"
+#include "llvm/Support/CodeGen.h"
+
+namespace llvm {
+class XtensaTargetMachine;
+class FunctionPass;
+
+FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM,
+ CodeGenOptLevel OptLevel);
+} // namespace llvm
+#endif // LLVM_LIB_TARGET_XTENSA_XTENSA_H
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index b953540be94de0b..460a15e808b3a40 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -35,6 +35,12 @@ def : Proc<"generic", []>;
include "XtensaRegisterInfo.td"
+//===----------------------------------------------------------------------===//
+// Calling Convention Description
+//===----------------------------------------------------------------------===//
+
+include "XtensaCallingConv.td"
+
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
new file mode 100644
index 000000000000000..fc681b1cbe8bd61
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -0,0 +1,41 @@
+//===- XtensaAsmPrinter.cpp Xtensa LLVM Assembly Printer ------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a printer that converts from our internal representation
+// of machine-dependent LLVM code to GAS-format Xtensa assembly language.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaAsmPrinter.h"
+#include "TargetInfo/XtensaTargetInfo.h"
+#include "XtensaMCInstLower.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCSectionELF.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/TargetRegistry.h"
+
+using namespace llvm;
+
+void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
+ XtensaMCInstLower Lower(MF->getContext(), *this);
+ MCInst LoweredMI;
+ Lower.lower(MI, LoweredMI);
+ EmitToStreamer(*OutStreamer, LoweredMI);
+}
+
+// Force static initialization.
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() {
+ RegisterAsmPrinter<XtensaAsmPrinter> A(getTheXtensaTarget());
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
new file mode 100644
index 000000000000000..37ead2ddb37f112
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -0,0 +1,42 @@
+//===- XtensaAsmPrinter.h - Xtensa LLVM Assembly Printer --------*- C++-*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Xtensa Assembly printer class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H
+
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+class MCStreamer;
+class MachineBasicBlock;
+class MachineInstr;
+class Module;
+class raw_ostream;
+
+class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter {
+ const MCSubtargetInfo *STI;
+
+public:
+ explicit XtensaAsmPrinter(TargetMachine &TM,
+ std::unique_ptr<MCStreamer> Streamer)
+ : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
+
+ StringRef getPassName() const override { return "Xtensa Assembly Printer"; }
+ void emitInstruction(const MachineInstr *MI) override;
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td
new file mode 100644
index 000000000000000..1026e7a9cea6875
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td
@@ -0,0 +1,30 @@
+//===- XtensaCallingConv.td - Xtensa Calling Conventions -*- tablegen ---*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// This describes the calling conventions for the Xtensa ABI.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Xtensa return value calling convention
+//===----------------------------------------------------------------------===//
+def RetCC_Xtensa : CallingConv<[
+ CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+ CCIfType<[f32], CCBitConvertToType<i32>>,
+
+ // First two return values go in a2, a3, a4, a5
+ CCIfType<[i32], CCAssignToReg<[A2, A3, A4, A5]>>,
+ CCIfType<[f32], CCAssignToReg<[A2, A3, A4, A5]>>,
+ CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>>
+]>;
+
+//===----------------------------------------------------------------------===//
+// Callee-saved register lists.
+//===----------------------------------------------------------------------===//
+
+def CSR_Xtensa : CalleeSavedRegs<(add A0, A12, A13, A14, A15)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
new file mode 100644
index 000000000000000..b201b99813ced13
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
@@ -0,0 +1,44 @@
+//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of TargetFrameLowering class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaFrameLowering.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaSubtarget.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/Function.h"
+
+using namespace llvm;
+
+XtensaFrameLowering::XtensaFrameLowering()
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0,
+ Align(4)) {}
+
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register. This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const {
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+ MFI.hasVarSizedObjects();
+}
+
+void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {}
+
+void XtensaFrameLowering::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {}
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
new file mode 100644
index 000000000000000..a5dfc83b940597d
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
@@ -0,0 +1,34 @@
+//===- XtensaFrameLowering.h - Define frame lowering for Xtensa --*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----------------------------------------------------------------------==//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H
+
+#include "llvm/CodeGen/TargetFrameLowering.h"
+
+namespace llvm {
+class XtensaTargetMachine;
+class XtensaSubtarget;
+
+class XtensaFrameLowering : public TargetFrameLowering {
+public:
+ XtensaFrameLowering();
+
+ bool hasFP(const MachineFunction &MF) const override;
+
+ /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
+ /// the function.
+ void emitPrologue(MachineFunction &, MachineBasicBlock &) const override;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+};
+
+} // namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
new file mode 100644
index 000000000000000..1c2263109bd850c
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -0,0 +1,81 @@
+//===- XtensaISelDAGToDAG.cpp - A dag to dag inst selector for Xtensa -----===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines an instruction selector for the Xtensa target.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Xtensa.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "xtensa-isel"
+
+namespace {
+
+class XtensaDAGToDAGISel : public SelectionDAGISel {
+public:
+ static char ID;
+
+ XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISel(ID, TM, OptLevel) {}
+
+ StringRef getPassName() const override {
+ return "Xtensa DAG->DAG Pattern Instruction Selection";
+ }
+
+ void Select(SDNode *Node) override;
+
+ bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
+ int Scale) {
+ report_fatal_error("MemReg address is not implemented yet");
+ }
+
+ bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 1);
+ }
+
+ bool selectMemRegAddrISH2(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 2);
+ }
+
+ bool selectMemRegAddrISH4(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 4);
+ }
+
+// Include the pieces autogenerated from the target description.
+#include "XtensaGenDAGISel.inc"
+}; // namespace
+} // end anonymous namespace
+
+char XtensaDAGToDAGISel::ID = 0;
+
+FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
+ CodeGenOptLevel OptLevel) {
+ return new XtensaDAGToDAGISel(TM, OptLevel);
+}
+
+void XtensaDAGToDAGISel::Select(SDNode *Node) {
+ SDLoc DL(Node);
+
+ // If we have a custom node, we already have selected!
+ if (Node->isMachineOpcode()) {
+ Node->setNodeId(-1);
+ return;
+ }
+
+ SelectCode(Node);
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
new file mode 100644
index 000000000000000..4e747731c48fbba
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -0,0 +1,330 @@
+//===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that Xtensa uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaISelLowering.h"
+#include "XtensaSubtarget.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "xtensa-lower"
+
+XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
+ const XtensaSubtarget &STI)
+ : TargetLowering(tm), Subtarget(STI) {
+ // Set up the register classes.
+ addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
+
+ // Set up special registers.
+ setStackPointerRegisterToSaveRestore(Xtensa::SP);
+
+ setSchedulingPreference(Sched::RegPressure);
+
+ setBooleanContents(ZeroOrOneBooleanContent);
+ setBooleanVectorContents(ZeroOrOneBooleanContent);
+
+ setMinFunctionAlignment(Align(4));
+
+ // Compute derived properties from the register classes
+ computeRegisterProperties(STI.getRegisterInfo());
+}
+
+//===----------------------------------------------------------------------===//
+// Calling conventions
+//===----------------------------------------------------------------------===//
+
+#include "XtensaGenCallingConv.inc"
+
+static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+ static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4,
+ Xtensa::A5, Xtensa::A6, Xtensa::A7};
+
+ if (ArgFlags.isByVal()) {
+ Align ByValAlign = ArgFlags.getNonZeroByValAlign();
+ unsigned ByValSize = ArgFlags.getByValSize();
+ if (ByValSize < 4) {
+ ByValSize = 4;
+ }
+ if (ByValAlign < Align(4)) {
+ ByValAlign = Align(4);
+ }
+ unsigned Offset = State.AllocateStack(ByValSize, ByValAlign);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
+ // Mark all unused registers as allocated to avoid misuse
+ // of such registers.
+ while (State.AllocateReg(IntRegs)) {
+ }
+ return false;
+ }
+
+ // Promote i8 and i16
+ if (LocVT == MVT::i8 || LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ unsigned Reg;
+
+ Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
+ bool needs64BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(8));
+ bool needs128BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(16));
+
+ if (ValVT == MVT::i32 || ValVT == MVT::f32) {
+ Reg = State.AllocateReg(IntRegs);
+ // If this is the first part of an i64 arg,
+ // the allocated register must be either A2, A4 or A6.
+ if (needs64BitAlign &&
+ (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7))
+ Reg = State.AllocateReg(IntRegs);
+ // arguments with 16byte alignment must be passed in the first register or
+ // passed via stack
+ if (needs128BitAlign && Reg != Xtensa::A2)
+ while ((Reg = State.AllocateReg(IntRegs))) {
+ }
+ LocVT = MVT::i32;
+ } else if (ValVT == MVT::f64) {
+ // Allocate int register and shadow next int register.
+ Reg = State.AllocateReg(IntRegs);
+ if (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)
+ Reg = State.AllocateReg(IntRegs);
+ State.AllocateReg(IntRegs);
+ LocVT = MVT::i32;
+ } else {
+ report_fatal_error("Cannot handle this ValVT.");
+ }
+
+ if (!Reg) {
+ unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
+ } else {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ }
+
+ return false;
+}
+
+CCAssignFn *XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
+ bool IsVarArg) const {
+ return CC_Xtensa_Custom;
+}
+
+// Value is a value of type VA.getValVT() that we need to copy into
+// the location described by VA. Return a copy of Value converted to
+// VA.getValVT(). The caller is responsible for handling indirect values.
+static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA,
+ SDValue Value) {
+ switch (VA.getLocInfo()) {
+ case CCValAssign::SExt:
+ return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
+ case CCValAssign::ZExt:
+ return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
+ case CCValAssign::AExt:
+ return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
+ case CCValAssign::BCvt:
+ return DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Value);
+ case CCValAssign::Full:
+ return Value;
+ default:
+ report_fatal_error("Unhandled getLocInfo()");
+ }
+}
+
+SDValue XtensaTargetLowering::LowerFormalArguments(
+ SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
+ SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+
+ // Used with vargs to acumulate store chains.
+ std::vector<SDValue> OutChains;
+
+ if (IsVarArg) {
+ report_fatal_error("Var arg not supported by FormalArguments Lowering");
+ }
+
+ // Assign locations to all of the incoming arguments.
+ SmallVector<CCValAssign, 16> ArgLocs;
+ CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
+ *DAG.getContext());
+
+ CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
+
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+ CCValAssign &VA = ArgLocs[i];
+ // Arguments stored on registers
+ if (VA.isRegLoc()) {
+ EVT RegVT = VA.getLocVT();
+ const TargetRegisterClass *RC;
+
+ if (RegVT == MVT::i32) {
+ RC = &Xtensa::ARRegClass;
+ } else
+ report_fatal_error("RegVT not supported by FormalArguments Lowering");
+
+ // Transform the arguments stored on
+ // physical registers into virtual ones
+ unsigned Register = MF.addLiveIn(VA.getLocReg(), RC);
+ SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Register, RegVT);
+
+ // If this is an 8 or 16-bit value, it has been passed promoted
+ // to 32 bits. Insert an assert[sz]ext to capture this, then
+ // truncate to the right size.
+ if (VA.getLocInfo() != CCValAssign::Full) {
+ unsigned Opcode = 0;
+ if (VA.getLocInfo() == CCValAssign::SExt)
+ Opcode = ISD::AssertSext;
+ else if (VA.getLocInfo() == CCValAssign::ZExt)
+ Opcode = ISD::AssertZext;
+ if (Opcode)
+ ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
+ DAG.getValueType(VA.getValVT()));
+ ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST
+ : ISD::TRUNCATE,
+ DL, VA.getValVT(), ArgValue);
+ }
+
+ InVals.push_back(ArgValue);
+
+ } else { // !VA.isRegLoc()
+ // sanity check
+ assert(VA.isMemLoc());
+
+ EVT ValVT = VA.getValVT();
+
+ // The stack pointer offset is relative to the caller stack frame.
+ int FI = MFI.CreateFixedObject(ValVT.getStoreSize(), VA.getLocMemOffset(),
+ true);
+
+ if (Ins[VA.getValNo()].Flags.isByVal()) {
+ // Assume that in this case load operation is created
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
+ InVals.push_back(FIN);
+ } else {
+ // Create load nodes to retrieve arguments from the stack
+ SDValue FIN =
+ DAG.getFrameIndex(FI, getFrameIndexTy(DAG.getDataLayout()));
+ InVals.push_back(DAG.getLoad(
+ ValVT, DL, Chain, FIN,
+ MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
+ }
+ }
+ }
+
+ // All stores are grouped in one node to allow the matching between
+ // the size of Ins and InVals. This only happens when on varg functions
+ if (!OutChains.empty()) {
+ OutChains.push_back(Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
+ }
+
+ return Chain;
+}
+
+bool XtensaTargetLowering::CanLowerReturn(
+ CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+ SmallVector<CCValAssign, 16> RVLocs;
+ CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
+ return CCInfo.CheckReturn(Outs, RetCC_Xtensa);
+}
+
+SDValue
+XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
+ const SDLoc &DL, SelectionDAG &DAG) const {
+ if (IsVarArg) {
+ report_fatal_error("VarArg not supported");
+ }
+
+ MachineFunction &MF = DAG.getMachineFunction();
+
+ // Assign locations to each returned value.
+ SmallVector<CCValAssign, 16> RetLocs;
+ CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
+ RetCCInfo.AnalyzeReturn(Outs, RetCC_Xtensa);
+
+ SDValue Glue;
+ // Quick exit for void returns
+ if (RetLocs.empty())
+ return DAG.getNode(XtensaISD::RET, DL, MVT::Other, Chain);
+
+ // Copy the result values into the output registers.
+ SmallVector<SDValue, 4> RetOps;
+ RetOps.push_back(Chain);
+ for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
+ CCValAssign &VA = RetLocs[I];
+ SDValue RetValue = OutVals[I];
+
+ // Make the return register live on exit.
+ assert(VA.isRegLoc() && "Can only return in registers!");
+
+ // Promote the value as required.
+ RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
+
+ // Chain and glue the copies together.
+ unsigned Reg = VA.getLocReg();
+ Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
+ Glue = Chain.getValue(1);
+ RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
+ }
+
+ // Update chain and glue.
+ RetOps[0] = Chain;
+ if (Glue.getNode())
+ RetOps.push_back(Glue);
+
+ return DAG.getNode(XtensaISD::RET, DL, MVT::Other, RetOps);
+}
+
+SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
+ SelectionDAG &DAG) const {
+ switch (Op.getOpcode()) {
+ default:
+ report_fatal_error("Unexpected node to lower");
+ }
+}
+
+const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
+#define OPCODE(NAME) \
+ case XtensaISD::NAME: \
+ return "XtensaISD::" #NAME
+ switch (Opcode) {
+ case XtensaISD::FIRST_NUMBER:
+ break;
+ case XtensaISD::RET:
+ return "XtensaISD::RET";
+ }
+ return NULL;
+#undef OPCODE
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
new file mode 100644
index 000000000000000..01ed42c84c3cdd6
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -0,0 +1,64 @@
+//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that Xtensa uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H
+
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
+
+namespace llvm {
+namespace XtensaISD {
+enum {
+ FIRST_NUMBER = ISD::BUILTIN_OP_END,
+ RET
+};
+}
+
+class XtensaSubtarget;
+
+class XtensaTargetLowering : public TargetLowering {
+public:
+ explicit XtensaTargetLowering(const TargetMachine &TM,
+ const XtensaSubtarget &STI);
+
+ const char *getTargetNodeName(unsigned Opcode) const override;
+ SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+ SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
+ bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &DL, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const override;
+
+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+ bool isVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context) const override;
+
+ SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
+ SelectionDAG &DAG) const override;
+
+private:
+ const XtensaSubtarget &Subtarget;
+
+ CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
+};
+
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
new file mode 100644
index 000000000000000..52a87fe4b934385
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -0,0 +1,27 @@
+//===- XtensaInstrInfo.cpp - Xtensa Instruction Information ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaInstrInfo.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+#define GET_INSTRINFO_CTOR_DTOR
+#include "XtensaGenInstrInfo.inc"
+
+using namespace llvm;
+
+XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti)
+ : XtensaGenInstrInfo(), RI(sti), STI(sti) {}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
new file mode 100644
index 000000000000000..7225886b2ce1198
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -0,0 +1,43 @@
+//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
+
+#include "Xtensa.h"
+#include "XtensaRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_INSTRINFO_HEADER
+
+#include "XtensaGenInstrInfo.inc"
+
+namespace llvm {
+
+class XtensaTargetMachine;
+class XtensaSubtarget;
+class XtensaInstrInfo : public XtensaGenInstrInfo {
+ const XtensaRegisterInfo RI;
+ XtensaSubtarget &STI;
+
+public:
+ XtensaInstrInfo(XtensaSubtarget &STI);
+
+ // Return the XtensaRegisterInfo, which this class owns.
+ const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 268a9943d8c1604..e9887601bd72a77 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -14,6 +14,7 @@
include "XtensaInstrFormats.td"
include "XtensaOperands.td"
+include "XtensaOperators.td"
//===----------------------------------------------------------------------===//
// Arithmetic & Logical instructions
@@ -238,6 +239,11 @@ def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label),
let imm16 = label;
}
+//extending loads
+def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
+
//===----------------------------------------------------------------------===//
// Conditional branch instructions
//===----------------------------------------------------------------------===//
@@ -426,7 +432,7 @@ let isReturn = 1, isTerminator = 1,
isBarrier = 1, Uses = [A0] in {
def RET : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),
- "ret", []> {
+ "ret", [(Xtensa_retflag)]> {
let m = 0x2;
let n = 0x0;
let s = 0;
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
new file mode 100644
index 000000000000000..5be72f92870e877
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
@@ -0,0 +1,62 @@
+//===- XtensaMCInstLower.cpp - Convert Xtensa MachineInstr to MCInst ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains code to lower Xtensa MachineInstrs to their corresponding
+// MCInst records.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaMCInstLower.h"
+#include "MCTargetDesc/XtensaMCExpr.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/IR/Mangler.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCStreamer.h"
+
+using namespace llvm;
+
+XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx,
+ XtensaAsmPrinter &asmPrinter)
+ : Ctx(ctx), Printer(asmPrinter) {}
+
+MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
+ unsigned Offset) const {
+ MachineOperand::MachineOperandType MOTy = MO.getType();
+
+ switch (MOTy) {
+ case MachineOperand::MO_Register:
+ // Ignore all implicit register operands.
+ if (MO.isImplicit())
+ break;
+ return MCOperand::createReg(MO.getReg());
+ case MachineOperand::MO_Immediate:
+ return MCOperand::createImm(MO.getImm() + Offset);
+ case MachineOperand::MO_RegisterMask:
+ break;
+ default:
+ report_fatal_error("unknown operand type");
+ }
+
+ return MCOperand();
+}
+
+void XtensaMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
+ OutMI.setOpcode(MI->getOpcode());
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ MCOperand MCOp = lowerOperand(MO);
+
+ if (MCOp.isValid())
+ OutMI.addOperand(MCOp);
+ }
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
new file mode 100644
index 000000000000000..2b238417ae3eba1
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
@@ -0,0 +1,43 @@
+//===- XtensaMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
+
+#include "XtensaAsmPrinter.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/DataTypes.h"
+
+namespace llvm {
+class MCContext;
+class MCInst;
+class MCOperand;
+class MCSymbol;
+class MachineInstr;
+class MachineOperand;
+class XtensaAsmPrinter;
+
+class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower {
+ MCContext &Ctx;
+ XtensaAsmPrinter &Printer;
+
+public:
+ XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter);
+
+ // Lower MachineInstr MI to MCInst OutMI.
+ void lower(const MachineInstr *MI, MCInst &OutMI) const;
+
+ // Return an MCOperand for MO. Return an empty operand if MO is implicit.
+ MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const;
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td
new file mode 100644
index 000000000000000..dce20ee189d2f98
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaOperators.td
@@ -0,0 +1,15 @@
+//===- XtensaOperators.td - Xtensa-specific operators ---------*- tblgen-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Node definitions
+//===----------------------------------------------------------------------===//
+def Xtensa_retflag: SDNode<"XtensaISD::RET", SDTNone,
+ [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
new file mode 100644
index 000000000000000..5cebe4a3346b256
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -0,0 +1,70 @@
+//===- XtensaRegisterInfo.cpp - Xtensa Register Information ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaRegisterInfo.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaSubtarget.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+#define DEBUG_TYPE "xtensa-reg-info"
+
+#define GET_REGINFO_TARGET_DESC
+#include "XtensaGenRegisterInfo.inc"
+
+using namespace llvm;
+
+XtensaRegisterInfo::XtensaRegisterInfo(const XtensaSubtarget &STI)
+ : XtensaGenRegisterInfo(Xtensa::A0), Subtarget(STI) {}
+
+const uint16_t *
+XtensaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+ return CSR_Xtensa_SaveList;
+}
+
+const uint32_t *
+XtensaRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID) const {
+ return CSR_Xtensa_RegMask;
+}
+
+BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
+
+ Reserved.set(Xtensa::A0);
+ if (TFI->hasFP(MF)) {
+ // Reserve frame pointer.
+ Reserved.set(getFrameRegister(MF));
+ }
+
+ // Reserve stack pointer.
+ Reserved.set(Xtensa::SP);
+ return Reserved;
+}
+
+bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, unsigned FIOperandNum,
+ RegScavenger *RS) const {
+ report_fatal_error("Eliminate frame index not supported yet");
+ return false;
+}
+
+Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+ const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
+ return TFI->hasFP(MF) ? (Xtensa::A15) : Xtensa::SP;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
new file mode 100644
index 000000000000000..4f5426acf7a5596
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
@@ -0,0 +1,56 @@
+//===-- XtensaRegisterInfo.h - Xtensa Register Information Impl -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
+
+#include "Xtensa.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#include "XtensaGenRegisterInfo.inc"
+
+namespace llvm {
+class TargetRegisterClass;
+class XtensaInstrInfo;
+class XtensaSubtarget;
+
+struct XtensaRegisterInfo : public XtensaGenRegisterInfo {
+public:
+ const XtensaSubtarget &Subtarget;
+
+ XtensaRegisterInfo(const XtensaSubtarget &STI);
+
+ bool requiresRegisterScavenging(const MachineFunction &MF) const override {
+ return true;
+ }
+
+ bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
+ return true;
+ }
+
+ const uint16_t *
+ getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
+ const uint32_t *getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID) const override;
+ BitVector getReservedRegs(const MachineFunction &MF) const override;
+ bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+ unsigned FIOperandNum,
+ RegScavenger *RS = nullptr) const override;
+ Register getFrameRegister(const MachineFunction &MF) const override;
+};
+
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
new file mode 100644
index 000000000000000..f76af66cac1efd5
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -0,0 +1,46 @@
+//===- XtensaSubtarget.cpp - Xtensa Subtarget Information -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Xtensa specific subclass of TargetSubtargetInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaSubtarget.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "xtensa-subtarget"
+
+#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
+#include "XtensaGenSubtargetInfo.inc"
+
+using namespace llvm;
+
+XtensaSubtarget &
+XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
+ StringRef CPUName = CPU;
+ if (CPUName.empty()) {
+ // set default cpu name
+ CPUName = "generic";
+ }
+
+ HasDensity = false;
+
+ // Parse features string.
+ ParseSubtargetFeatures(CPUName, CPUName, FS);
+ return *this;
+}
+
+XtensaSubtarget::XtensaSubtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const TargetMachine &TM)
+ : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
+ TSInfo(), FrameLowering() {}
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
new file mode 100644
index 000000000000000..0fca21957adeb69
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -0,0 +1,72 @@
+//===-- XtensaSubtarget.h - Define Subtarget for the Xtensa ----*- C++ -*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Xtensa specific subclass of TargetSubtargetInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
+
+#include "XtensaFrameLowering.h"
+#include "XtensaISelLowering.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
+
+#define GET_SUBTARGETINFO_HEADER
+#include "XtensaGenSubtargetInfo.inc"
+
+namespace llvm {
+class StringRef;
+
+class XtensaSubtarget : public XtensaGenSubtargetInfo {
+private:
+ Triple TargetTriple;
+ XtensaInstrInfo InstrInfo;
+ XtensaTargetLowering TLInfo;
+ SelectionDAGTargetInfo TSInfo;
+ XtensaFrameLowering FrameLowering;
+
+ // Enabled Xtensa Density extension
+ bool HasDensity;
+
+ XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
+
+public:
+ XtensaSubtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const TargetMachine &TM);
+
+ const TargetFrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const XtensaInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+ const XtensaRegisterInfo *getRegisterInfo() const override {
+ return &InstrInfo.getRegisterInfo();
+ }
+
+ const XtensaTargetLowering *getTargetLowering() const override {
+ return &TLInfo;
+ }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
+ }
+
+ bool hasDensity() const { return HasDensity; }
+
+ // Automatically generated by tblgen.
+ void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index c891ecd9c0c3fc9..d61533e0c496762 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -52,7 +52,8 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
- TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
+ TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
+ Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();
}
@@ -64,6 +65,31 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
CodeGenOptLevel OL, bool JIT)
: XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
+const XtensaSubtarget *
+XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
+ return &Subtarget;
+}
+
+namespace {
+/// Xtensa Code Generator Pass Configuration Options.
+class XtensaPassConfig : public TargetPassConfig {
+public:
+ XtensaPassConfig(XtensaTargetMachine &TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
+
+ XtensaTargetMachine &getXtensaTargetMachine() const {
+ return getTM<XtensaTargetMachine>();
+ }
+
+ bool addInstSelector() override;
+};
+} // end anonymous namespace
+
+bool XtensaPassConfig::addInstSelector() {
+ addPass(createXtensaISelDag(getXtensaTargetMachine(), getOptLevel()));
+ return false;
+}
+
TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {
- return new TargetPassConfig(*this, PM);
+ return new XtensaPassConfig(*this, PM);
}
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index dd76f45b3bb717a..be0886f2a9b0fec 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -15,6 +15,7 @@
#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H
#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H
+#include "XtensaSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
@@ -36,10 +37,15 @@ class XtensaTargetMachine : public LLVMTargetMachine {
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
+ const XtensaSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const XtensaSubtarget *getSubtargetImpl(const Function &F) const override;
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+protected:
+ XtensaSubtarget Subtarget;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/Xtensa/alu.ll b/llvm/test/CodeGen/Xtensa/alu.ll
new file mode 100644
index 000000000000000..c044b3eb90ee6ac
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/alu.ll
@@ -0,0 +1,158 @@
+; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=XTENSA
+
+; Register-immediate instructions
+
+define i32 @addi(i32 %a) nounwind {
+; XTENSA-LABEL: addi:
+; XTENSA: addi a2, a2, 1
+; XTENSA: ret
+ %1 = add i32 %a, 1
+ ret i32 %1
+}
+
+define i32 @addmi(i32 %a) nounwind {
+; XTENSA-LABEL: addmi:
+; XTENSA: addmi a2, a2, 32512
+; XTENSA: ret
+ %1 = add i32 %a, 32512
+ ret i32 %1
+}
+
+define i32 @shrai(i32 %a) nounwind {
+; XTENSA-LABEL: shrai:
+; XTENSA: srai a2, a2, 4
+; XTENSA: ret
+ %1 = ashr i32 %a, 4
+ ret i32 %1
+}
+
+define i32 @slli(i32 %a) nounwind {
+; XTENSA-LABEL: slli:
+; XTENSA: slli a2, a2, 4
+; XTENSA: ret
+ %1 = shl i32 %a, 4
+ ret i32 %1
+}
+
+define i32 @srli(i32 %a) nounwind {
+; XTENSA-LABEL: srli:
+; XTENSA: srli a2, a2, 4
+; XTENSA: ret
+ %1 = lshr i32 %a, 4
+ ret i32 %1
+}
+
+define i32 @movi(i32 %a) nounwind {
+; XTENSA-LABEL: movi:
+; XTENSA: movi a8, 2047
+; XTENSA: add a2, a2, a8
+; XTENSA: ret
+ %1 = add i32 %a, 2047
+ ret i32 %1
+}
+
+; Register-register instructions
+
+define i32 @add(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: add:
+; XTENSA: add a2, a2, a3
+; XTENSA: ret
+ %1 = add i32 %a, %b
+ ret i32 %1
+}
+
+define i32 @addx2(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: addx2:
+; XTENSA: addx2 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 1
+ %2 = add i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @addx4(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: addx4:
+; XTENSA: addx4 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 2
+ %2 = add i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @addx8(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: addx8:
+; XTENSA: addx8 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 3
+ %2 = add i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @sub(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: sub:
+; XTENSA: sub a2, a2, a3
+; XTENSA: ret
+ %1 = sub i32 %a, %b
+ ret i32 %1
+}
+
+define i32 @subx2(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: subx2:
+; XTENSA: subx2 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 1
+ %2 = sub i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @subx4(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: subx4:
+; XTENSA: subx4 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 2
+ %2 = sub i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @subx8(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: subx8:
+; XTENSA: subx8 a2, a2, a3
+; XTENSA: ret
+ %1 = shl i32 %a, 3
+ %2 = sub i32 %1, %b
+ ret i32 %2
+}
+
+define i32 @xor(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: xor:
+; XTENSA: xor a2, a2, a3
+; XTENSA: ret
+ %1 = xor i32 %a, %b
+ ret i32 %1
+}
+
+define i32 @or(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: or:
+; XTENSA: or a2, a2, a3
+; XTENSA: ret
+ %1 = or i32 %a, %b
+ ret i32 %1
+}
+
+define i32 @and(i32 %a, i32 %b) nounwind {
+; XTENSA-LABEL: and:
+; XTENSA: and a2, a2, a3
+; XTENSA: ret
+ %1 = and i32 %a, %b
+ ret i32 %1
+}
+
+define i32 @neg(i32 %a) nounwind {
+; XTENSA-LABEL: neg:
+; XTENSA: neg a2, a2
+; XTENSA: ret
+ %1 = sub i32 0, %a
+ ret i32 %1
+}
+
>From d7a0f08ffdae18bc83cbed8c1ceea6cd9d74d9a7 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Wed, 26 Jul 2023 00:34:01 +0300
Subject: [PATCH 2/5] [Xtensa] Codegen support for memory operations.
---
llvm/lib/Target/Xtensa/CMakeLists.txt | 1 +
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 51 +++++++++++++-
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 7 ++
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 69 +++++++++++++++++++
llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 19 +++++
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 52 +++++++++++++-
llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 4 ++
llvm/lib/Target/Xtensa/XtensaUtils.cpp | 60 ++++++++++++++++
llvm/lib/Target/Xtensa/XtensaUtils.h | 27 ++++++++
llvm/test/CodeGen/Xtensa/stack-access.ll | 36 ++++++++++
10 files changed, 323 insertions(+), 3 deletions(-)
create mode 100644 llvm/lib/Target/Xtensa/XtensaUtils.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaUtils.h
create mode 100644 llvm/test/CodeGen/Xtensa/stack-access.ll
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index bb1e09cb0652ecf..301820e5d5ecbf2 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -24,6 +24,7 @@ add_llvm_target(XtensaCodeGen
XtensaRegisterInfo.cpp
XtensaSubtarget.cpp
XtensaTargetMachine.cpp
+ XtensaUtils.cpp
LINK_COMPONENTS
AsmPrinter
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 1c2263109bd850c..b46f03b32e84d8f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -14,9 +14,11 @@
#include "Xtensa.h"
#include "XtensaTargetMachine.h"
+#include "XtensaUtils.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -41,7 +43,54 @@ class XtensaDAGToDAGISel : public SelectionDAGISel {
bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
int Scale) {
- report_fatal_error("MemReg address is not implemented yet");
+ EVT ValTy = Addr.getValueType();
+
+ // if Address is FI, get the TargetFrameIndex.
+ if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+ Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
+
+ return true;
+ }
+
+ if (TM.isPositionIndependent()) {
+ DiagnosticInfoUnsupported Diag(
+ CurDAG->getMachineFunction().getFunction(),
+ "PIC relocations are not supported ",
+ Addr.getDebugLoc());
+ CurDAG->getContext()->diagnose(Diag);
+ }
+
+ if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
+ Addr.getOpcode() == ISD::TargetGlobalAddress))
+ return false;
+
+ // Addresses of the form FI+const or FI|const
+ bool Valid = false;
+ if (CurDAG->isBaseWithConstantOffset(Addr)) {
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+ int64_t OffsetVal = CN->getSExtValue();
+
+ Valid = isValidAddrOffset(Scale, OffsetVal);
+
+ if (Valid) {
+ // If the first operand is a FI, get the TargetFI Node
+ if (FrameIndexSDNode *FIN =
+ dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+ else
+ Base = Addr.getOperand(0);
+
+ Offset =
+ CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy);
+ return true;
+ }
+ }
+
+ // Last case
+ Base = Addr;
+ Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
+ return true;
}
bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) {
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 4e747731c48fbba..73267a39cfa94b8 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -46,6 +46,13 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
setMinFunctionAlignment(Align(4));
+ // No sign extend instructions for i1
+ for (MVT VT : MVT::integer_valuetypes()) {
+ setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
+ }
+
// Compute derived properties from the register classes
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index 52a87fe4b934385..10cf4f5d00cafdc 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -15,6 +15,7 @@
#include "XtensaInstrInfo.h"
#include "XtensaTargetMachine.h"
#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -23,5 +24,73 @@
using namespace llvm;
+static inline const MachineInstrBuilder &
+addFrameReference(const MachineInstrBuilder &MIB, int FI) {
+ MachineInstr *MI = MIB;
+ MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFrameInfo &MFFrame = MF.getFrameInfo();
+ const MCInstrDesc &MCID = MI->getDesc();
+ MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
+ if (MCID.mayLoad())
+ Flags |= MachineMemOperand::MOLoad;
+ if (MCID.mayStore())
+ Flags |= MachineMemOperand::MOStore;
+ int64_t Offset = 0;
+ Align Alignment = MFFrame.getObjectAlign(FI);
+
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI, Offset),
+ Flags, MFFrame.getObjectSize(FI), Alignment);
+ return MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
+}
+
XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti)
: XtensaGenInstrInfo(), RI(sti), STI(sti) {}
+
+void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, MCRegister DestReg,
+ MCRegister SrcReg, bool KillSrc) const {
+ // when we are copying a phys reg we want the bits for fp
+ if (Xtensa::ARRegClass.contains(DestReg, SrcReg))
+ BuildMI(MBB, MBBI, DL, get(Xtensa::OR), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ else
+ report_fatal_error("Impossible reg-to-reg copy");
+}
+
+void XtensaInstrInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIdx, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg) const {
+ DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+ unsigned LoadOpcode, StoreOpcode;
+ getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx);
+ addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
+ .addReg(SrcReg, getKillRegState(isKill)),
+ FrameIdx);
+}
+
+void XtensaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIdx,
+ const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI,
+ Register VReg) const {
+ DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+ unsigned LoadOpcode, StoreOpcode;
+ getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx);
+ addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg), FrameIdx);
+}
+
+void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
+ unsigned &LoadOpcode,
+ unsigned &StoreOpcode,
+ int64_t offset) const {
+ if (RC == &Xtensa::ARRegClass) {
+ LoadOpcode = Xtensa::L32I;
+ StoreOpcode = Xtensa::S32I;
+ } else
+ report_fatal_error("Unsupported regclass to load or store");
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
index 7225886b2ce1198..d09108ef9128e77 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -37,6 +37,25 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
// Return the XtensaRegisterInfo, which this class owns.
const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
+
+ void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
+ bool KillSrc) const override;
+ void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI,
+ Register VReg) const override;
+ void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, Register DestReg,
+ int FrameIdx, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI,
+ Register VReg) const override;
+
+ // Get the load and store opcodes for a given register class and offset.
+ void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,
+ unsigned &StoreOpcode, int64_t offset) const;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
index 5cebe4a3346b256..a218af8c4d4179c 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -15,6 +15,9 @@
#include "XtensaRegisterInfo.h"
#include "XtensaInstrInfo.h"
#include "XtensaSubtarget.h"
+#include "XtensaUtils.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
@@ -57,11 +60,56 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
+bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
+ unsigned OpNo, int FrameIndex,
+ uint64_t StackSize,
+ int64_t SPOffset) const {
+ MachineInstr &MI = *II;
+ unsigned FrameReg = Xtensa::SP;
+
+ // Calculate final offset.
+ // - There is no need to change the offset if the frame object is one of the
+ // following: an outgoing argument, pointer to a dynamically allocated
+ // stack space or a $gp restore location,
+ // - If the frame object is any of the following, its offset must be adjusted
+ // by adding the size of the stack:
+ // incoming argument, callee-saved register location or local variable.
+ bool IsKill = false;
+ int64_t Offset =
+ SPOffset + (int64_t)StackSize + MI.getOperand(OpNo + 1).getImm();
+
+ LLVM_DEBUG(errs() << "Offset : " << Offset << "\n"
+ << "<--------->\n");
+
+ bool Valid = isValidAddrOffset(MI, Offset);
+
+ // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
+ // field.
+ if (!MI.isDebugValue() && !Valid) {
+ report_fatal_error("Load immediate not supported yet");
+ }
+
+ MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
+ MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
+
+ return false;
+}
+
bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {
- report_fatal_error("Eliminate frame index not supported yet");
- return false;
+ MachineInstr &MI = *II;
+ MachineFunction &MF = *MI.getParent()->getParent();
+ LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
+ errs() << "<--------->\n"
+ << MI);
+ int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
+ uint64_t stackSize = MF.getFrameInfo().getStackSize();
+ int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
+ LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
+ << "spOffset : " << spOffset << "\n"
+ << "stackSize : " << stackSize << "\n");
+ return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
}
Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
index 4f5426acf7a5596..4305dca9f4421a8 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
@@ -49,6 +49,10 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo {
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
+
+private:
+ bool eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
+ int FrameIndex, uint64_t StackSize, int64_t SPOffset) const;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaUtils.cpp b/llvm/lib/Target/Xtensa/XtensaUtils.cpp
new file mode 100644
index 000000000000000..0f3b8847b49c99a
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaUtils.cpp
@@ -0,0 +1,60 @@
+//===--- XtensaUtils.cpp ---- Xtensa Utility Functions ----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains miscellaneous utility functions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaUtils.h"
+
+namespace llvm {
+
+// Check address offset for load/store instructions
+// The offset should be multiple of scale
+bool isValidAddrOffset(int Scale, int64_t OffsetVal) {
+ bool Valid = false;
+
+ switch (Scale) {
+ case 1:
+ Valid = (OffsetVal >= 0 && OffsetVal <= 255);
+ break;
+ case 2:
+ Valid = (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);
+ break;
+ case 4:
+ Valid = (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);
+ break;
+ default:
+ break;
+ }
+ return Valid;
+}
+
+// Check address offset for load/store instructions
+bool isValidAddrOffset(MachineInstr &MI, int64_t Offset) {
+ int Scale = 0;
+
+ switch (MI.getOpcode()) {
+ case Xtensa::L8UI:
+ case Xtensa::S8I:
+ Scale = 1;
+ break;
+ case Xtensa::L16SI:
+ case Xtensa::L16UI:
+ case Xtensa::S16I:
+ Scale = 2;
+ break;
+ default:
+ // assume that MI is 32-bit load/store operation
+ Scale = 4;
+ break;
+ }
+ return isValidAddrOffset(Scale, Offset);
+}
+
+} // namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaUtils.h b/llvm/lib/Target/Xtensa/XtensaUtils.h
new file mode 100644
index 000000000000000..def93fa8bd4e132
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaUtils.h
@@ -0,0 +1,27 @@
+//===--- XtensaUtils.h ---- Xtensa Utility Functions ------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains miscellaneous utility functions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H
+
+#include "XtensaInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+
+namespace llvm {
+// Check address offset for load/store instructions
+// The offset should be multiple of scale
+bool isValidAddrOffset(int Scale, int64_t OffsetVal);
+
+// Check address offset for load/store instructions
+bool isValidAddrOffset(MachineInstr &MI, int64_t Offset);
+} // namespace llvm
+#endif // LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H
diff --git a/llvm/test/CodeGen/Xtensa/stack-access.ll b/llvm/test/CodeGen/Xtensa/stack-access.ll
new file mode 100644
index 000000000000000..1d589450c2b53be
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/stack-access.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=xtensa -O0 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=XTENSA
+
+define i8 @loadi8(i8 %a) {
+; XTENSA-LABEL: loadi8:
+; XTENSA: s8i a2, a1, 3
+; XTENSA: l8ui a2, a1, 3
+; XTENSA: ret
+ %b = alloca i8, align 1
+ store i8 %a, ptr %b, align 1
+ %1 = load i8, ptr %b, align 1
+ ret i8 %1
+}
+
+define i16 @loadi16(i16 %a) {
+; XTENSA-LABEL: loadi16:
+; XTENSA: s16i a2, a1, 2
+; XTENSA: l16ui a2, a1, 2
+; XTENSA: ret
+ %b = alloca i16, align 2
+ store i16 %a, ptr %b, align 2
+ %1 = load i16, ptr %b, align 2
+ ret i16 %1
+}
+
+define i32 @loadi32(i32 %a) {
+; XTENSA-LABEL: loadi32:
+; XTENSA: s32i a2, a1, 0
+; XTENSA: l32i a2, a1, 0
+; XTENSA: ret
+ %b = alloca i32, align 4
+ store i32 %a, ptr %b, align 4
+ %1 = load i32, ptr %b, align 4
+ ret i32 %1
+}
+
>From 43bf22af1a48e0d312fd8b3a2bab2295a56bca79 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Tue, 12 Dec 2023 01:59:34 +0300
Subject: [PATCH 3/5] [Xtensa] Add initial implementation of the Constant Pool.
---
llvm/lib/Target/Xtensa/CMakeLists.txt | 1 +
.../Target/Xtensa/XtensaConstantPoolValue.cpp | 210 ++++++++++++++
.../Target/Xtensa/XtensaConstantPoolValue.h | 267 ++++++++++++++++++
3 files changed, 478 insertions(+)
create mode 100644 llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 301820e5d5ecbf2..f0abf3e550a124e 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -16,6 +16,7 @@ add_public_tablegen_target(XtensaCommonTableGen)
add_llvm_target(XtensaCodeGen
XtensaAsmPrinter.cpp
+ XtensaConstantPoolValue.cpp
XtensaFrameLowering.cpp
XtensaInstrInfo.cpp
XtensaISelDAGToDAG.cpp
diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
new file mode 100644
index 000000000000000..2845a5ac849d66d
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
@@ -0,0 +1,210 @@
+//===- XtensaConstantPoolValue.cpp - Xtensa constantpool value ------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Xtensa specific constantpool value class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaConstantPoolValue.h"
+#include "llvm/ADT/FoldingSet.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cstdlib>
+using namespace llvm;
+
+XtensaConstantPoolValue::XtensaConstantPoolValue(
+ Type *Ty, unsigned id, XtensaCP::XtensaCPKind kind,
+ XtensaCP::XtensaCPModifier modifier)
+ : MachineConstantPoolValue(Ty), LabelId(id), Kind(kind),
+ Modifier(modifier) {}
+
+XtensaConstantPoolValue::XtensaConstantPoolValue(
+ LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind kind,
+ XtensaCP::XtensaCPModifier modifier)
+ : MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(id),
+ Kind(kind), Modifier(modifier) {}
+
+XtensaConstantPoolValue::~XtensaConstantPoolValue() {}
+
+StringRef XtensaConstantPoolValue::getModifierText() const {
+ switch (Modifier) {
+ case XtensaCP::no_modifier:
+ return "";
+ case XtensaCP::TPOFF:
+ return "@TPOFF";
+ }
+ report_fatal_error("Unknown modifier!");
+}
+
+int XtensaConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) {
+ report_fatal_error("Shouldn't be calling this directly!");
+}
+
+void XtensaConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+ ID.AddInteger(LabelId);
+}
+
+bool XtensaConstantPoolValue::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ if (ACPV->Kind == Kind) {
+ if (ACPV->LabelId == LabelId)
+ return true;
+ }
+ return false;
+}
+
+void XtensaConstantPoolValue::dump() const { errs() << " " << *this; }
+
+void XtensaConstantPoolValue::print(raw_ostream &O) const {}
+
+//===----------------------------------------------------------------------===//
+// XtensaConstantPoolConstant
+//===----------------------------------------------------------------------===//
+
+XtensaConstantPoolConstant::XtensaConstantPoolConstant(
+ const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind)
+ : XtensaConstantPoolValue((Type *)C->getType(), ID, Kind),
+ CVal(C) {}
+
+XtensaConstantPoolConstant *
+XtensaConstantPoolConstant::Create(const Constant *C, unsigned ID,
+ XtensaCP::XtensaCPKind Kind) {
+ return new XtensaConstantPoolConstant(C, ID, Kind);
+}
+
+const BlockAddress *XtensaConstantPoolConstant::getBlockAddress() const {
+ return dyn_cast_or_null<BlockAddress>(CVal);
+}
+
+int XtensaConstantPoolConstant::getExistingMachineCPValue(
+ MachineConstantPool *CP, Align Alignment) {
+ return getExistingMachineCPValueImpl<XtensaConstantPoolConstant>(CP,
+ Alignment);
+}
+
+bool XtensaConstantPoolConstant::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ const XtensaConstantPoolConstant *ACPC =
+ dyn_cast<XtensaConstantPoolConstant>(ACPV);
+ return ACPC && ACPC->CVal == CVal &&
+ XtensaConstantPoolValue::hasSameValue(ACPV);
+}
+
+void XtensaConstantPoolConstant::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+ ID.AddPointer(CVal);
+ XtensaConstantPoolValue::addSelectionDAGCSEId(ID);
+}
+
+void XtensaConstantPoolConstant::print(raw_ostream &O) const {
+ O << CVal->getName();
+ XtensaConstantPoolValue::print(O);
+}
+
+XtensaConstantPoolSymbol::XtensaConstantPoolSymbol(
+ LLVMContext &C, const char *s, unsigned id, bool PrivLinkage,
+ XtensaCP::XtensaCPModifier Modifier)
+ : XtensaConstantPoolValue(C, id, XtensaCP::CPExtSymbol, Modifier), S(s),
+ PrivateLinkage(PrivLinkage) {}
+
+XtensaConstantPoolSymbol *
+XtensaConstantPoolSymbol::Create(LLVMContext &C, const char *s, unsigned ID,
+ bool PrivLinkage,
+ XtensaCP::XtensaCPModifier Modifier)
+
+{
+ return new XtensaConstantPoolSymbol(C, s, ID, PrivLinkage, Modifier);
+}
+
+int XtensaConstantPoolSymbol::getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) {
+ return getExistingMachineCPValueImpl<XtensaConstantPoolSymbol>(CP, Alignment);
+}
+
+bool XtensaConstantPoolSymbol::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ const XtensaConstantPoolSymbol *ACPS =
+ dyn_cast<XtensaConstantPoolSymbol>(ACPV);
+ return ACPS && ACPS->S == S && XtensaConstantPoolValue::hasSameValue(ACPV);
+}
+
+void XtensaConstantPoolSymbol::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+ ID.AddString(S);
+ XtensaConstantPoolValue::addSelectionDAGCSEId(ID);
+}
+
+void XtensaConstantPoolSymbol::print(raw_ostream &O) const {
+ O << S;
+ XtensaConstantPoolValue::print(O);
+}
+
+XtensaConstantPoolMBB::XtensaConstantPoolMBB(LLVMContext &C,
+ const MachineBasicBlock *mbb,
+ unsigned id)
+ : XtensaConstantPoolValue(C, 0, XtensaCP::CPMachineBasicBlock),
+ MBB(mbb) {}
+
+XtensaConstantPoolMBB *
+XtensaConstantPoolMBB::Create(LLVMContext &C, const MachineBasicBlock *mbb,
+ unsigned idx) {
+ return new XtensaConstantPoolMBB(C, mbb, idx);
+}
+
+int XtensaConstantPoolMBB::getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) {
+ return getExistingMachineCPValueImpl<XtensaConstantPoolMBB>(CP, Alignment);
+}
+
+bool XtensaConstantPoolMBB::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ const XtensaConstantPoolMBB *ACPMBB = dyn_cast<XtensaConstantPoolMBB>(ACPV);
+ return ACPMBB && ACPMBB->MBB == MBB &&
+ XtensaConstantPoolValue::hasSameValue(ACPV);
+}
+
+void XtensaConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+ ID.AddPointer(MBB);
+ XtensaConstantPoolValue::addSelectionDAGCSEId(ID);
+}
+
+void XtensaConstantPoolMBB::print(raw_ostream &O) const {
+ O << "BB#" << MBB->getNumber();
+ XtensaConstantPoolValue::print(O);
+}
+
+XtensaConstantPoolJumpTable::XtensaConstantPoolJumpTable(LLVMContext &C,
+ unsigned idx)
+ : XtensaConstantPoolValue(C, 0, XtensaCP::CPJumpTable), IDX(idx) {}
+
+XtensaConstantPoolJumpTable *XtensaConstantPoolJumpTable::Create(LLVMContext &C,
+ unsigned idx) {
+ return new XtensaConstantPoolJumpTable(C, idx);
+}
+
+int XtensaConstantPoolJumpTable::getExistingMachineCPValue(
+ MachineConstantPool *CP, Align Alignment) {
+ return getExistingMachineCPValueImpl<XtensaConstantPoolJumpTable>(CP,
+ Alignment);
+}
+
+bool XtensaConstantPoolJumpTable::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ const XtensaConstantPoolJumpTable *ACPJT =
+ dyn_cast<XtensaConstantPoolJumpTable>(ACPV);
+ return ACPJT && ACPJT->IDX == IDX &&
+ XtensaConstantPoolValue::hasSameValue(ACPV);
+}
+
+void XtensaConstantPoolJumpTable::addSelectionDAGCSEId(FoldingSetNodeID &ID) {}
+
+void XtensaConstantPoolJumpTable::print(raw_ostream &O) const {
+ O << "JT" << IDX;
+ XtensaConstantPoolValue::print(O);
+}
+
diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
new file mode 100644
index 000000000000000..9aaf9776fe601ed
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
@@ -0,0 +1,267 @@
+//===- XtensaConstantPoolValue.h - Xtensa constantpool value ----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Xtensa specific constantpool value class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H
+
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/ErrorHandling.h"
+#include <cstddef>
+#include <string>
+#include <vector>
+
+namespace llvm {
+
+class BlockAddress;
+class Constant;
+class GlobalValue;
+class LLVMContext;
+class MachineBasicBlock;
+
+namespace XtensaCP {
+enum XtensaCPKind {
+ CPExtSymbol,
+ CPBlockAddress,
+ CPMachineBasicBlock,
+ CPJumpTable
+};
+
+enum XtensaCPModifier {
+ no_modifier, // None
+ TPOFF // Thread Pointer Offset
+};
+} // namespace XtensaCP
+
+/// XtensaConstantPoolValue - Xtensa specific constantpool value. This is used
+/// to represent PC-relative displacement between the address of the load
+/// instruction and the constant being loaded.
+class XtensaConstantPoolValue : public MachineConstantPoolValue {
+ unsigned LabelId; // Label id of the load.
+ XtensaCP::XtensaCPKind Kind; // Kind of constant.
+ XtensaCP::XtensaCPModifier Modifier; // Symbol name modifier
+ //(for example Global Variable name)
+
+protected:
+ XtensaConstantPoolValue(
+ Type *Ty, unsigned id, XtensaCP::XtensaCPKind Kind,
+ XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier);
+
+ XtensaConstantPoolValue(
+ LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind Kind,
+ XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier);
+
+ template <typename Derived>
+ int getExistingMachineCPValueImpl(MachineConstantPool *CP, Align Alignment) {
+ const std::vector<MachineConstantPoolEntry> &Constants = CP->getConstants();
+ for (unsigned i = 0, e = Constants.size(); i != e; ++i) {
+ if (Constants[i].isMachineConstantPoolEntry() &&
+ (Constants[i].getAlign() >= Alignment)) {
+ XtensaConstantPoolValue *CPV =
+ (XtensaConstantPoolValue *)Constants[i].Val.MachineCPVal;
+ if (Derived *APC = dyn_cast<Derived>(CPV))
+ if (cast<Derived>(this)->equals(APC))
+ return i;
+ }
+ }
+
+ return -1;
+ }
+
+public:
+ ~XtensaConstantPoolValue() override;
+
+ XtensaCP::XtensaCPModifier getModifier() const { return Modifier; }
+ bool hasModifier() const { return Modifier != XtensaCP::no_modifier; }
+ StringRef getModifierText() const;
+
+ unsigned getLabelId() const { return LabelId; }
+ void setLabelId(unsigned id) { LabelId = id; }
+
+ bool isExtSymbol() const { return Kind == XtensaCP::CPExtSymbol; }
+ bool isBlockAddress() const { return Kind == XtensaCP::CPBlockAddress; }
+ bool isMachineBasicBlock() const {
+ return Kind == XtensaCP::CPMachineBasicBlock;
+ }
+ bool isJumpTable() const { return Kind == XtensaCP::CPJumpTable; }
+
+ int getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) override;
+
+ void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+ /// hasSameValue - Return true if this Xtensa constpool value can share the
+ /// same constantpool entry as another Xtensa constpool value.
+ virtual bool hasSameValue(XtensaConstantPoolValue *ACPV);
+
+ bool equals(const XtensaConstantPoolValue *A) const {
+ return this->LabelId == A->LabelId && this->Modifier == A->Modifier;
+ }
+
+ void print(raw_ostream &O) const override;
+ void print(raw_ostream *O) const {
+ if (O)
+ print(*O);
+ }
+ void dump() const;
+};
+
+inline raw_ostream &operator<<(raw_ostream &O,
+ const XtensaConstantPoolValue &V) {
+ V.print(O);
+ return O;
+}
+
+/// XtensaConstantPoolConstant - Xtensa-specific constant pool values for
+/// Constants (for example BlockAddresses).
+class XtensaConstantPoolConstant : public XtensaConstantPoolValue {
+ const Constant *CVal; // Constant being loaded.
+
+ XtensaConstantPoolConstant(const Constant *C, unsigned ID,
+ XtensaCP::XtensaCPKind Kind);
+
+public:
+ static XtensaConstantPoolConstant *Create(const Constant *C, unsigned ID,
+ XtensaCP::XtensaCPKind Kind);
+
+ const BlockAddress *getBlockAddress() const;
+
+ int getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) override;
+
+ /// hasSameValue - Return true if this Xtensa constpool value can share the
+ /// same constantpool entry as another Xtensa constpool value.
+ bool hasSameValue(XtensaConstantPoolValue *ACPV) override;
+
+ void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+ void print(raw_ostream &O) const override;
+ static bool classof(const XtensaConstantPoolValue *APV) {
+ return APV->isBlockAddress();
+ }
+
+ bool equals(const XtensaConstantPoolConstant *A) const {
+ return CVal == A->CVal && XtensaConstantPoolValue::equals(A);
+ }
+};
+
+
+/// XtensaConstantPoolSymbol - Xtensa-specific constantpool values for external
+/// symbols.
+class XtensaConstantPoolSymbol : public XtensaConstantPoolValue {
+ const std::string S; // ExtSymbol being loaded.
+ bool PrivateLinkage;
+
+ XtensaConstantPoolSymbol(
+ LLVMContext &C, const char *s, unsigned id, bool PrivLinkage,
+ XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier);
+
+public:
+ static XtensaConstantPoolSymbol *
+ Create(LLVMContext &C, const char *s, unsigned ID, bool PrivLinkage,
+ XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier);
+
+ const char *getSymbol() const { return S.c_str(); }
+
+ int getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) override;
+
+ void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+ /// hasSameValue - Return true if this Xtensa constpool value can share the
+ /// same constantpool entry as another Xtensa constpool value.
+ bool hasSameValue(XtensaConstantPoolValue *ACPV) override;
+
+ bool isPrivateLinkage() { return PrivateLinkage; }
+
+ void print(raw_ostream &O) const override;
+
+ static bool classof(const XtensaConstantPoolValue *ACPV) {
+ return ACPV->isExtSymbol();
+ }
+
+ bool equals(const XtensaConstantPoolSymbol *A) const {
+ return S == A->S && XtensaConstantPoolValue::equals(A);
+ }
+};
+
+/// XtensaConstantPoolMBB - Xtensa-specific constantpool value of a machine
+/// basic block.
+class XtensaConstantPoolMBB : public XtensaConstantPoolValue {
+ const MachineBasicBlock *MBB; // Machine basic block.
+
+ XtensaConstantPoolMBB(LLVMContext &C, const MachineBasicBlock *mbb,
+ unsigned id);
+
+public:
+ static XtensaConstantPoolMBB *
+ Create(LLVMContext &C, const MachineBasicBlock *mbb, unsigned ID);
+
+ const MachineBasicBlock *getMBB() const { return MBB; }
+
+ int getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) override;
+
+ void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+ /// hasSameValue - Return true if this Xtensa constpool value can share the
+ /// same constantpool entry as another Xtensa constpool value.
+ bool hasSameValue(XtensaConstantPoolValue *ACPV) override;
+
+ void print(raw_ostream &O) const override;
+
+ static bool classof(const XtensaConstantPoolValue *ACPV) {
+ return ACPV->isMachineBasicBlock();
+ }
+
+ bool equals(const XtensaConstantPoolMBB *A) const {
+ return MBB == A->MBB && XtensaConstantPoolValue::equals(A);
+ }
+};
+
+/// XtensaConstantPoolJumpTable - Xtensa-specific constantpool values for Jump
+/// Table symbols.
+class XtensaConstantPoolJumpTable : public XtensaConstantPoolValue {
+ unsigned IDX; // Jump Table Index.
+
+ XtensaConstantPoolJumpTable(LLVMContext &C, unsigned idx);
+
+public:
+ static XtensaConstantPoolJumpTable *Create(LLVMContext &C, unsigned idx);
+
+ unsigned getIndex() const { return IDX; }
+
+ int getExistingMachineCPValue(MachineConstantPool *CP,
+ Align Alignment) override;
+
+ void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+ /// hasSameValue - Return true if this Xtensa constpool value can share the
+ /// same constantpool entry as another Xtensa constpool value.
+ bool hasSameValue(XtensaConstantPoolValue *ACPV) override;
+
+ void print(raw_ostream &O) const override;
+
+ static bool classof(const XtensaConstantPoolValue *ACPV) {
+ return ACPV->isJumpTable();
+ }
+
+ bool equals(const XtensaConstantPoolJumpTable *A) const {
+ return IDX == A->IDX && XtensaConstantPoolValue::equals(A);
+ }
+};
+
+} // namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H */
>From 3f58dbedad927083dbb82e1eadc8e0876f4946bd Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Wed, 13 Dec 2023 01:00:13 +0300
Subject: [PATCH 4/5] [Xtensa] Implement constanpool lowering.
Implement assembler representation of the Constant Pool. Implement
asm literal parsing and lowering integer Constant.
---
.../Xtensa/AsmParser/XtensaAsmParser.cpp | 135 +++++++++++++++++-
.../Target/Xtensa/MCTargetDesc/CMakeLists.txt | 1 +
.../MCTargetDesc/XtensaMCTargetDesc.cpp | 26 +++-
.../MCTargetDesc/XtensaTargetStreamer.cpp | 87 +++++++++++
.../MCTargetDesc/XtensaTargetStreamer.h | 46 ++++++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 76 ++++++++++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 1 +
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 60 +++++++-
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 8 ++
llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 3 +
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 39 +++++
llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 7 +
llvm/lib/Target/Xtensa/XtensaOperands.td | 2 +-
llvm/lib/Target/Xtensa/XtensaOperators.td | 8 ++
llvm/test/CodeGen/Xtensa/constantpool.ll | 28 ++++
llvm/test/MC/Xtensa/Core/invalid.s | 4 -
llvm/test/MC/Xtensa/directive-literal.s | 42 ++++++
17 files changed, 561 insertions(+), 12 deletions(-)
create mode 100644 llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
create mode 100644 llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
create mode 100644 llvm/test/CodeGen/Xtensa/constantpool.ll
create mode 100644 llvm/test/MC/Xtensa/directive-literal.s
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index 3f808298527f8fc..9fd05ee96a9290d 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -8,7 +8,9 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/XtensaMCExpr.h"
#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "MCTargetDesc/XtensaTargetStreamer.h"
#include "TargetInfo/XtensaTargetInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSwitch.h"
@@ -22,6 +24,7 @@
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Casting.h"
@@ -35,6 +38,12 @@ class XtensaAsmParser : public MCTargetAsmParser {
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
+ XtensaTargetStreamer &getTargetStreamer() {
+ MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
+ return static_cast<XtensaTargetStreamer &>(TS);
+ }
+
+ bool ParseDirective(AsmToken DirectiveID) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -45,6 +54,9 @@ class XtensaAsmParser : public MCTargetAsmParser {
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
+ bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
// Auto-generated instruction matching functions
#define GET_ASSEMBLER_HEADER
#include "XtensaGenAsmMatcher.inc"
@@ -62,6 +74,7 @@ class XtensaAsmParser : public MCTargetAsmParser {
return ParseStatus::NoMatch;
}
ParseStatus parsePCRelTarget(OperandVector &Operands);
+ bool parseLiteralDirective(SMLoc L);
public:
enum XtensaMatchResultTy {
@@ -148,7 +161,13 @@ struct XtensaOperand : public MCParsedAsmOperand {
bool isImm12() const { return isImm(-2048, 2047); }
- bool isImm12m() const { return isImm(-2048, 2047); }
+ // Convert MOVI to literal load, when immediate is not in range (-2048, 2047)
+ bool isImm12m() const {
+ if (Kind == Immediate)
+ return true;
+
+ return false;
+ }
bool isOffset4m32() const {
return isImm(0, 60) &&
@@ -348,6 +367,67 @@ static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
return Loc;
}
+bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
+ MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ Inst.setLoc(IDLoc);
+ const unsigned Opcode = Inst.getOpcode();
+ switch (Opcode) {
+ case Xtensa::L32R: {
+ const MCSymbolRefExpr *OpExpr =
+ (const MCSymbolRefExpr *)Inst.getOperand(1).getExpr();
+ XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None;
+ const MCExpr *NewOpExpr = XtensaMCExpr::create(OpExpr, Kind, getContext());
+ Inst.getOperand(1).setExpr(NewOpExpr);
+ } break;
+ case Xtensa::MOVI: {
+ XtensaTargetStreamer &TS = this->getTargetStreamer();
+
+ // Expand MOVI operand
+ if (!Inst.getOperand(1).isExpr()) {
+ uint64_t ImmOp64 = Inst.getOperand(1).getImm();
+ int32_t Imm = ImmOp64;
+ if ((Imm < -2048) || (Imm > 2047)) {
+ XtensaTargetStreamer &TS = this->getTargetStreamer();
+ MCInst TmpInst;
+ TmpInst.setLoc(IDLoc);
+ TmpInst.setOpcode(Xtensa::L32R);
+ const MCExpr *Value = MCConstantExpr::create(ImmOp64, getContext());
+ MCSymbol *Sym = getContext().createTempSymbol();
+ const MCExpr *Expr = MCSymbolRefExpr::create(
+ Sym, MCSymbolRefExpr::VK_None, getContext());
+ const MCExpr *OpExpr = XtensaMCExpr::create(
+ Expr, XtensaMCExpr::VK_Xtensa_None, getContext());
+ TmpInst.addOperand(Inst.getOperand(0));
+ MCOperand Op1 = MCOperand::createExpr(OpExpr);
+ TmpInst.addOperand(Op1);
+ TS.emitLiteral(Sym, Value, IDLoc);
+ Inst = TmpInst;
+ }
+ } else {
+ MCInst TmpInst;
+ TmpInst.setLoc(IDLoc);
+ TmpInst.setOpcode(Xtensa::L32R);
+ const MCExpr *Value = Inst.getOperand(1).getExpr();
+ MCSymbol *Sym = getContext().createTempSymbol();
+ const MCExpr *Expr =
+ MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+ const MCExpr *OpExpr = XtensaMCExpr::create(
+ Expr, XtensaMCExpr::VK_Xtensa_None, getContext());
+ TmpInst.addOperand(Inst.getOperand(0));
+ MCOperand Op1 = MCOperand::createExpr(OpExpr);
+ TmpInst.addOperand(Op1);
+ Inst = TmpInst;
+ TS.emitLiteral(Sym, Value, IDLoc);
+ }
+ } break;
+ default:
+ break;
+ }
+
+ return true;
+}
+
bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
@@ -361,6 +441,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
default:
break;
case Match_Success:
+ processInstruction(Inst, IDLoc, Out, STI);
Inst.setLoc(IDLoc);
Out.emitInstruction(Inst, getSTI());
return false;
@@ -686,6 +767,58 @@ bool XtensaAsmParser::ParseInstruction(ParseInstructionInfo &Info,
return false;
}
+bool XtensaAsmParser::parseLiteralDirective(SMLoc L) {
+ MCAsmParser &Parser = getParser();
+ MCSymbol *Sym;
+ const MCExpr *Value;
+ SMLoc LiteralLoc = getLexer().getLoc();
+ XtensaTargetStreamer &TS = this->getTargetStreamer();
+
+ if (Parser.parseExpression(Value))
+ return true;
+
+ const MCSymbolRefExpr *SE = dyn_cast<MCSymbolRefExpr>(Value);
+ if (!SE)
+ return Error(LiteralLoc, "literal label must be a symbol");
+ else {
+ Sym = getContext().getOrCreateSymbol(SE->getSymbol().getName());
+ }
+
+ if (Parser.parseToken(AsmToken::Comma, "expected comma"))
+ return true;
+
+ SMLoc OpcodeLoc = getLexer().getLoc();
+ if (parseOptionalToken(AsmToken::EndOfStatement))
+ return Error(OpcodeLoc, "expected value");
+
+ if (Parser.parseExpression(Value))
+ return true;
+
+ TS.emitLiteral(Sym, Value, LiteralLoc);
+
+ return false;
+}
+
+bool XtensaAsmParser::ParseDirective(AsmToken DirectiveID) {
+ StringRef IDVal = DirectiveID.getString();
+ SMLoc Loc = getLexer().getLoc();
+
+ if (IDVal == ".literal_position") {
+ XtensaTargetStreamer &TS = this->getTargetStreamer();
+ TS.emitLiteralPosition();
+ Lex();
+ return false;
+ }
+
+ if (IDVal == ".literal") {
+ parseLiteralDirective(Loc);
+ Lex();
+ return false;
+ }
+
+ return true;
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmParser() {
RegisterMCAsmParser<XtensaAsmParser> X(getTheXtensaTarget());
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
index 6841b44f9d569cd..dc12863394c7ad0 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
@@ -6,6 +6,7 @@ add_llvm_component_library(LLVMXtensaDesc
XtensaMCCodeEmitter.cpp
XtensaMCExpr.cpp
XtensaMCTargetDesc.cpp
+ XtensaTargetStreamer.cpp
LINK_COMPONENTS
MC
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
index 48674d15bdfbe27..8914ebf658cc434 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
@@ -10,6 +10,7 @@
#include "XtensaMCTargetDesc.h"
#include "XtensaInstPrinter.h"
#include "XtensaMCAsmInfo.h"
+#include "XtensaTargetStreamer.h"
#include "TargetInfo/XtensaTargetInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -63,16 +64,29 @@ createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS);
}
+static MCTargetStreamer *
+createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
+ MCInstPrinter *InstPrint, bool isVerboseAsm) {
+ return new XtensaTargetAsmStreamer(S, OS);
+}
+
+static MCTargetStreamer *
+createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
+ return new XtensaTargetELFStreamer(S);
+}
+
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() {
// Register the MCAsmInfo.
- TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(), createXtensaMCAsmInfo);
+ TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(),
+ createXtensaMCAsmInfo);
// Register the MCCodeEmitter.
TargetRegistry::RegisterMCCodeEmitter(getTheXtensaTarget(),
createXtensaMCCodeEmitter);
// Register the MCInstrInfo.
- TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(), createXtensaMCInstrInfo);
+ TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(),
+ createXtensaMCInstrInfo);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(getTheXtensaTarget(),
@@ -89,4 +103,12 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() {
// Register the MCAsmBackend.
TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(),
createXtensaMCAsmBackend);
+
+ // Register the asm target streamer.
+ TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(),
+ createXtensaAsmTargetStreamer);
+
+ // Register the ELF target streamer.
+ TargetRegistry::RegisterObjectTargetStreamer(
+ getTheXtensaTarget(), createXtensaObjectTargetStreamer);
}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
new file mode 100644
index 000000000000000..4163e64de48f091
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
@@ -0,0 +1,87 @@
+//===-- XtensaTargetStreamer.cpp - Xtensa Target Streamer Methods ---------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides Xtensa specific target streamer methods.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaTargetStreamer.h"
+#include "XtensaInstPrinter.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCSectionELF.h"
+#include "llvm/Support/FormattedStream.h"
+
+using namespace llvm;
+
+XtensaTargetStreamer::XtensaTargetStreamer(MCStreamer &S)
+ : MCTargetStreamer(S) {}
+
+XtensaTargetAsmStreamer::XtensaTargetAsmStreamer(MCStreamer &S,
+ formatted_raw_ostream &OS)
+ : XtensaTargetStreamer(S), OS(OS) {}
+
+void XtensaTargetAsmStreamer::emitLiteral(MCSymbol *LblSym, const MCExpr *Value,
+ SMLoc L) {
+ const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
+
+ OS << "\t.literal\t";
+ LblSym->print(OS, MAI);
+ OS << ", ";
+ Value->print(OS, MAI);
+ OS << '\n';
+}
+
+void XtensaTargetAsmStreamer::emitLiteralPosition() {
+ OS << "\t.literal_position\n";
+}
+
+XtensaTargetELFStreamer::XtensaTargetELFStreamer(MCStreamer &S)
+ : XtensaTargetStreamer(S) {}
+
+static std::string getLiteralSectionName(std::string CSectionName) {
+ std::size_t Pos = CSectionName.find(".text");
+ std::string SectionName;
+ if (Pos != std::string::npos) {
+ if (Pos > 0)
+ SectionName = CSectionName.substr(0, Pos + 5);
+ else
+ SectionName = "";
+ SectionName += ".literal";
+ SectionName += CSectionName.substr(Pos + 5);
+ } else {
+ SectionName = CSectionName;
+ SectionName += ".literal";
+ }
+ return SectionName;
+}
+
+void XtensaTargetELFStreamer::emitLiteral(MCSymbol *LblSym, const MCExpr *Value,
+ SMLoc L) {
+ MCContext &Context = getStreamer().getContext();
+ MCStreamer &OutStreamer = getStreamer();
+ MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly();
+ std::string SectionName = getLiteralSectionName(CS->getName().str());
+
+ MCSection *ConstSection = Context.getELFSection(
+ SectionName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC);
+
+ OutStreamer.pushSection();
+ OutStreamer.switchSection(ConstSection);
+ OutStreamer.emitLabel(LblSym, L);
+ OutStreamer.emitValue(Value, 4, L);
+ OutStreamer.popSection();
+}
+
+MCELFStreamer &XtensaTargetELFStreamer::getStreamer() {
+ return static_cast<MCELFStreamer &>(Streamer);
+}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
new file mode 100644
index 000000000000000..a7d8b6dd9c792b5
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
@@ -0,0 +1,46 @@
+//===-- XtensaTargetStreamer.h - Xtensa Target Streamer --------*- C++ -*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H
+
+#include "llvm/MC/MCELFStreamer.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/SMLoc.h"
+
+namespace llvm {
+class formatted_raw_ostream;
+
+class XtensaTargetStreamer : public MCTargetStreamer {
+public:
+ XtensaTargetStreamer(MCStreamer &S);
+ virtual void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) = 0;
+ virtual void emitLiteralPosition() = 0;
+};
+
+class XtensaTargetAsmStreamer : public XtensaTargetStreamer {
+ formatted_raw_ostream &OS;
+
+public:
+ XtensaTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
+ void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) override;
+ void emitLiteralPosition() override;
+};
+
+class XtensaTargetELFStreamer : public XtensaTargetStreamer {
+public:
+ XtensaTargetELFStreamer(MCStreamer &S);
+ MCELFStreamer &getStreamer();
+ void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) override;
+ void emitLiteralPosition() override {}
+};
+} // end namespace llvm
+
+#endif
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
index fc681b1cbe8bd61..855bc99f0abd5c8 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -16,7 +16,9 @@
#include "XtensaAsmPrinter.h"
#include "TargetInfo/XtensaTargetInfo.h"
#include "XtensaMCInstLower.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/MC/MCExpr.h"
@@ -35,6 +37,80 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
EmitToStreamer(*OutStreamer, LoweredMI);
}
+/// EmitConstantPool - Print to the current output stream assembly
+/// representations of the constants in the constant pool MCP. This is
+/// used to print out constants which have been "spilled to memory" by
+/// the code generator.
+void XtensaAsmPrinter::emitConstantPool() {
+ const Function &F = MF->getFunction();
+ const MachineConstantPool *MCP = MF->getConstantPool();
+ const std::vector<MachineConstantPoolEntry> &CP = MCP->getConstants();
+ if (CP.empty())
+ return;
+
+ for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+ const MachineConstantPoolEntry &CPE = CP[i];
+
+ if (i == 0) {
+ if (OutStreamer->hasRawTextSupport()) {
+ OutStreamer->switchSection(
+ getObjFileLowering().SectionForGlobal(&F, TM));
+ OutStreamer->emitRawText(StringRef("\t.literal_position\n"));
+ } else {
+ MCSectionELF *CS =
+ (MCSectionELF *)getObjFileLowering().SectionForGlobal(&F, TM);
+ std::string CSectionName = CS->getName().str();
+ std::size_t Pos = CSectionName.find(".text");
+ std::string SectionName;
+ if (Pos != std::string::npos) {
+ if (Pos > 0)
+ SectionName = CSectionName.substr(0, Pos + 5);
+ else
+ SectionName = "";
+ SectionName += ".literal";
+ SectionName += CSectionName.substr(Pos + 5);
+ } else {
+ SectionName = CSectionName;
+ SectionName += ".literal";
+ }
+
+ MCSectionELF *S =
+ OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS,
+ ELF::SHF_EXECINSTR | ELF::SHF_ALLOC);
+ S->setAlignment(Align(4));
+ OutStreamer->switchSection(S);
+ }
+ }
+
+ if (CPE.isMachineConstantPoolEntry()) {
+ report_fatal_error("This constantpool type is not supported yet");
+ } else {
+ MCSymbol *LblSym = GetCPISymbol(i);
+ // TODO find a better way to check whether we emit data to .s file
+ if (OutStreamer->hasRawTextSupport()) {
+ std::string str("\t.literal ");
+ str += LblSym->getName();
+ str += ", ";
+ const Constant *C = CPE.Val.ConstVal;
+
+ if (const auto *CFP = dyn_cast<ConstantFP>(C)) {
+ str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true);
+ } else if (const auto *CI = dyn_cast<ConstantInt>(C)) {
+ str += toString(CI->getValue(), 10, true);
+ } else {
+ report_fatal_error(
+ "This constant type is not supported yet in constantpool");
+ }
+
+ OutStreamer->emitRawText(StringRef(str));
+ } else {
+ OutStreamer->emitLabel(LblSym);
+ emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal);
+ }
+ }
+ }
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() {
RegisterAsmPrinter<XtensaAsmPrinter> A(getTheXtensaTarget());
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
index 37ead2ddb37f112..d9b8e8ed2b64ba6 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter {
StringRef getPassName() const override { return "Xtensa Assembly Printer"; }
void emitInstruction(const MachineInstr *MI) override;
+ void emitConstantPool() override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 73267a39cfa94b8..6e8951591d3e794 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -33,6 +33,7 @@ using namespace llvm;
XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
const XtensaSubtarget &STI)
: TargetLowering(tm), Subtarget(STI) {
+ MVT PtrVT = MVT::i32;
// Set up the register classes.
addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
@@ -46,6 +47,9 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
setMinFunctionAlignment(Align(4));
+ setOperationAction(ISD::Constant, MVT::i32, Custom);
+ setOperationAction(ISD::Constant, MVT::i64, Expand);
+
// No sign extend instructions for i1
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
@@ -53,6 +57,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
}
+ setOperationAction(ISD::ConstantPool, PtrVT, Custom);
+
// Compute derived properties from the register classes
computeRegisterProperties(STI.getRegisterInfo());
}
@@ -314,9 +320,57 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
return DAG.getNode(XtensaISD::RET, DL, MVT::Other, RetOps);
}
+SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
+ SelectionDAG &DAG) const {
+ const ConstantSDNode *CN = cast<ConstantSDNode>(Op);
+ SDLoc DL(CN);
+ APInt apval = CN->getAPIntValue();
+ int64_t value = apval.getSExtValue();
+ if (Op.getValueType() == MVT::i32) {
+ // Check if use node maybe lowered to the MOVI instruction
+ if (value > -2048 && value <= 2047)
+ return Op;
+ // Check if use node maybe lowered to the ADDMI instruction
+ SDNode &OpNode = *Op.getNode();
+ if ((OpNode.hasOneUse() && OpNode.use_begin()->getOpcode() == ISD::ADD) &&
+ (value >= -32768) && (value <= 32512) && ((value & 0xff) == 0))
+ return Op;
+ Type *Ty = Type::getInt32Ty(*DAG.getContext());
+ Constant *CV = ConstantInt::get(Ty, value);
+ SDValue CP = DAG.getConstantPool(CV, MVT::i32);
+ return CP;
+ }
+ return Op;
+}
+
+SDValue XtensaTargetLowering::getAddrPCRel(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ EVT Ty = Op.getValueType();
+ return DAG.getNode(XtensaISD::PCREL_WRAPPER, DL, Ty, Op);
+}
+
+SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP,
+ SelectionDAG &DAG) const {
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
+ SDValue Result;
+ if (!CP->isMachineConstantPoolEntry()) {
+ Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),
+ CP->getOffset());
+ } else {
+ report_fatal_error("This constantpool type is not supported yet");
+ }
+
+ return getAddrPCRel(Result, DAG);
+}
+
SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
+ case ISD::Constant:
+ return LowerImmediate(Op, DAG);
+ case ISD::ConstantPool:
+ return LowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
default:
report_fatal_error("Unexpected node to lower");
}
@@ -327,10 +381,8 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
case XtensaISD::NAME: \
return "XtensaISD::" #NAME
switch (Opcode) {
- case XtensaISD::FIRST_NUMBER:
- break;
- case XtensaISD::RET:
- return "XtensaISD::RET";
+ OPCODE(RET);
+ OPCODE(PCREL_WRAPPER);
}
return NULL;
#undef OPCODE
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index 01ed42c84c3cdd6..79a48ace444f1ac 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -24,6 +24,9 @@ namespace llvm {
namespace XtensaISD {
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
+ // Wraps a TargetGlobalAddress that should be loaded using PC-relative
+ // accesses. Operand 0 is the address.
+ PCREL_WRAPPER,
RET
};
}
@@ -56,6 +59,11 @@ class XtensaTargetLowering : public TargetLowering {
private:
const XtensaSubtarget &Subtarget;
+ SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
+
+ SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const;
+
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
};
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index e9887601bd72a77..3d2cd67d5742e0d 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -239,6 +239,9 @@ def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label),
let imm16 = label;
}
+// pcrel addr loading using L32R
+def : Pat<(Xtensa_pcrel_wrapper tconstpool : $in), (L32R tconstpool : $in)>;
+
//extending loads
def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
index 5be72f92870e877..b7a7c02ac2b5e78 100644
--- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
@@ -28,6 +28,43 @@ XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx,
XtensaAsmPrinter &asmPrinter)
: Ctx(ctx), Printer(asmPrinter) {}
+MCSymbol *
+XtensaMCInstLower::GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
+ // Create a symbol for the name.
+ return Printer.GetCPISymbol(MO.getIndex());
+}
+
+MCOperand
+XtensaMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
+ MachineOperand::MachineOperandType MOTy,
+ unsigned Offset) const {
+ const MCSymbol *Symbol;
+ XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None;
+
+ switch (MOTy) {
+ case MachineOperand::MO_ConstantPoolIndex:
+ Symbol = GetConstantPoolIndexSymbol(MO);
+ Offset += MO.getOffset();
+ break;
+ default:
+ report_fatal_error("<unknown operand type>");
+ }
+
+ const MCExpr *ME =
+ MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
+ ME = XtensaMCExpr::create(ME, Kind, Ctx);
+
+ if (Offset) {
+ // Assume offset is never negative.
+ assert(Offset > 0);
+
+ const MCConstantExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx);
+ ME = MCBinaryExpr::createAdd(ME, OffsetExpr, Ctx);
+ }
+
+ return MCOperand::createExpr(ME);
+}
+
MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
unsigned Offset) const {
MachineOperand::MachineOperandType MOTy = MO.getType();
@@ -42,6 +79,8 @@ MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
return MCOperand::createImm(MO.getImm() + Offset);
case MachineOperand::MO_RegisterMask:
break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ return LowerSymbolOperand(MO, MOTy, Offset);
default:
report_fatal_error("unknown operand type");
}
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
index 2b238417ae3eba1..32a0ad86a385094 100644
--- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
@@ -37,6 +37,13 @@ class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower {
// Return an MCOperand for MO. Return an empty operand if MO is implicit.
MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const;
+
+private:
+ MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
+
+ MCOperand LowerSymbolOperand(const MachineOperand &MO,
+ MachineOperand::MachineOperandType MOTy,
+ unsigned Offset) const;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td
index 7a1a2e86e8c20fa..f41081f9bf2f968 100644
--- a/llvm/lib/Target/Xtensa/XtensaOperands.td
+++ b/llvm/lib/Target/Xtensa/XtensaOperands.td
@@ -195,7 +195,7 @@ def jumptarget : Operand<OtherVT> {
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
}
-def L32Rtarget : Operand<OtherVT> {
+def L32Rtarget : Operand<i32> {
let PrintMethod = "printL32RTarget";
let EncoderMethod = "getL32RTargetEncoding";
let DecoderMethod = "decodeL32ROperand";
diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td
index dce20ee189d2f98..db295b8dd9d7c68 100644
--- a/llvm/lib/Target/Xtensa/XtensaOperators.td
+++ b/llvm/lib/Target/Xtensa/XtensaOperators.td
@@ -7,9 +7,17 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// Type profiles
+//===----------------------------------------------------------------------===//
+def SDT_XtensaWrapPtr : SDTypeProfile<1, 1,
+ [SDTCisSameAs<0, 1>,
+ SDTCisPtrTy<0>]>;
//===----------------------------------------------------------------------===//
// Node definitions
//===----------------------------------------------------------------------===//
def Xtensa_retflag: SDNode<"XtensaISD::RET", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+
+def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, []>;
diff --git a/llvm/test/CodeGen/Xtensa/constantpool.ll b/llvm/test/CodeGen/Xtensa/constantpool.ll
new file mode 100644
index 000000000000000..9b380d2c37b9e00
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/constantpool.ll
@@ -0,0 +1,28 @@
+; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+; Test placement of the i32,i64, float and double constants in constantpool
+
+define dso_local i32 @const_i32() #0 {
+; CHECK: .literal_position
+; CHECK-NEXT: .literal .LCPI0_0, 74565
+; CHECK-LABEL: const_i32:
+; CHECK: l32r a2, .LCPI0_0
+ %1 = alloca i32, align 4
+ store i32 74565, ptr %1, align 4
+ %2 = load i32, ptr %1, align 4
+ ret i32 %2
+}
+
+define dso_local i64 @const_int64() #0 {
+; CHECK: .literal_position
+; CHECK-NEXT: .literal .LCPI1_0, 305419896
+; CHECK-NEXT: .literal .LCPI1_1, -1859959449
+; CHECK-LABEL: const_int64:
+; CHECK: l32r a3, .LCPI1_0
+; CHECK: l32r a2, .LCPI1_1
+ %1 = alloca i64, align 8
+ store i64 1311768467302729063, ptr %1, align 8
+ %2 = load i64, ptr %1, align 8
+ ret i64 %2
+}
diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s
index d3d8fba8169a6d2..c7473e90c10ba37 100644
--- a/llvm/test/MC/Xtensa/Core/invalid.s
+++ b/llvm/test/MC/Xtensa/Core/invalid.s
@@ -4,10 +4,6 @@ LBL0:
# Out of range immediates
-# imm12m
-movi a1, 3000
-# CHECK: :[[#@LINE-1]]:10: error: expected immediate in range [-2048, 2047]
-
# imm8
addi a1, a2, 300
# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127]
diff --git a/llvm/test/MC/Xtensa/directive-literal.s b/llvm/test/MC/Xtensa/directive-literal.s
new file mode 100644
index 000000000000000..269cf20ed45eb2a
--- /dev/null
+++ b/llvm/test/MC/Xtensa/directive-literal.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=xtensa -filetype obj -o - %s \
+# RUN: | llvm-readobj -S --sd - \
+# RUN: | FileCheck -check-prefix=CHECK-LITERAL %s
+
+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+ .text
+ .literal_position
+ .literal .LCPI0_0, 305419896
+ .literal .LCPI1_0, ext_var
+ .global test_literal
+ .p2align 2
+ .type test_literal, at function
+test_literal:
+ l32r a2, .LCPI0_0
+ l32r a3, .LCPI1_0
+ movi a4, 30000
+ movi a5, 1000
+ ret
+
+# CHECK-LITERAL: Section {
+# CHECK-LITERAL: Name: .literal
+# CHECK-LITERAL: SectionData (
+# CHECK-LITERAL: 0000: 78563412 00000000 30750000
+# CHECK-LITERAL: )
+# CHECK-LITERAL: }
+
+# CHECK-INST: .literal_position
+# CHECK-INST: .literal .LCPI0_0, 305419896
+# CHECK-INST: .literal .LCPI1_0, ext_var
+# CHECK-INST: .global test_literal
+# CHECK-INST: .p2align 2
+# CHECK-INST: .type test_literal, at function
+# CHECK-INST: test_literal:
+# CHECK-INST: l32r a2, .LCPI0_0
+# CHECK-INST: l32r a3, .LCPI1_0
+# CHECK-INST: .literal .Ltmp0, 30000
+# CHECK-INST: l32r a4, .Ltmp0
+# CHECK-INST: movi a5, 1000
+# CHECK-INST: ret
+
>From 6f375b3c1bfcefdb8fe217efa381bf2cf8f757d3 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Wed, 13 Dec 2023 22:28:47 +0300
Subject: [PATCH 5/5] [Xtensa] Implement lowering constant FP and blockaddress.
---
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 118 ++++++++++++++----
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 3 +
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 46 ++++++-
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 +
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 9 ++
llvm/test/CodeGen/Xtensa/constantpool.ll | 52 ++++++++
6 files changed, 203 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
index 855bc99f0abd5c8..cf770ca289e7005 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#include "XtensaAsmPrinter.h"
+#include "XtensaConstantPoolValue.h"
#include "TargetInfo/XtensaTargetInfo.h"
#include "XtensaMCInstLower.h"
#include "llvm/ADT/StringExtras.h"
@@ -30,6 +31,17 @@
using namespace llvm;
+static MCSymbolRefExpr::VariantKind
+getModifierVariantKind(XtensaCP::XtensaCPModifier Modifier) {
+ switch (Modifier) {
+ case XtensaCP::no_modifier:
+ return MCSymbolRefExpr::VK_None;
+ case XtensaCP::TPOFF:
+ return MCSymbolRefExpr::VK_TPOFF;
+ }
+ report_fatal_error("Invalid XtensaCPModifier!");
+}
+
void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
XtensaMCInstLower Lower(MF->getContext(), *this);
MCInst LoweredMI;
@@ -37,6 +49,85 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
EmitToStreamer(*OutStreamer, LoweredMI);
}
+void XtensaAsmPrinter::emitMachineConstantPoolValue(
+ MachineConstantPoolValue *MCPV) {
+ XtensaConstantPoolValue *ACPV = static_cast<XtensaConstantPoolValue *>(MCPV);
+
+ MCSymbol *MCSym;
+ if (ACPV->isBlockAddress()) {
+ const BlockAddress *BA =
+ cast<XtensaConstantPoolConstant>(ACPV)->getBlockAddress();
+ MCSym = GetBlockAddressSymbol(BA);
+ } else {
+ report_fatal_error(
+ "This constant type is not supported yet in constantpool");
+ }
+
+ MCSymbol *LblSym = GetCPISymbol(ACPV->getLabelId());
+ // TODO find a better way to check whether we emit data to .s file
+ if (OutStreamer->hasRawTextSupport()) {
+ std::string SymName("\t.literal ");
+ SymName += LblSym->getName();
+ SymName += ", ";
+ SymName += MCSym->getName();
+
+ StringRef Modifier = ACPV->getModifierText();
+ SymName += Modifier;
+
+ OutStreamer->emitRawText(StringRef(SymName));
+ } else {
+ MCSymbolRefExpr::VariantKind VK =
+ getModifierVariantKind(ACPV->getModifier());
+
+ if (ACPV->getModifier() != XtensaCP::no_modifier) {
+ std::string SymName(MCSym->getName());
+ MCSym = GetExternalSymbolSymbol(StringRef(SymName));
+ }
+
+ const MCExpr *Expr = MCSymbolRefExpr::create(MCSym, VK, OutContext);
+ uint64_t Size = getDataLayout().getTypeAllocSize(ACPV->getType());
+ OutStreamer->emitCodeAlignment(
+ Align(4), OutStreamer->getContext().getSubtargetInfo());
+ OutStreamer->emitLabel(LblSym);
+ OutStreamer->emitValue(Expr, Size);
+ }
+}
+
+void XtensaAsmPrinter::emitMachineConstantPoolEntry(
+ const MachineConstantPoolEntry &CPE, int i) {
+ if (CPE.isMachineConstantPoolEntry()) {
+ XtensaConstantPoolValue *ACPV =
+ static_cast<XtensaConstantPoolValue *>(CPE.Val.MachineCPVal);
+ ACPV->setLabelId(i);
+ emitMachineConstantPoolValue(CPE.Val.MachineCPVal);
+ } else {
+ MCSymbol *LblSym = GetCPISymbol(i);
+ // TODO find a better way to check whether we emit data to .s file
+ if (OutStreamer->hasRawTextSupport()) {
+ std::string str("\t.literal ");
+ str += LblSym->getName();
+ str += ", ";
+ const Constant *C = CPE.Val.ConstVal;
+
+ if (const auto *CFP = dyn_cast<ConstantFP>(C)) {
+ str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true);
+ } else if (const auto *CI = dyn_cast<ConstantInt>(C)) {
+ str += toString(CI->getValue(), 10, true);
+ } else {
+ report_fatal_error(
+ "This constant type is not supported yet in constantpool");
+ }
+
+ OutStreamer->emitRawText(StringRef(str));
+ } else {
+ OutStreamer->emitCodeAlignment(
+ Align(4), OutStreamer->getContext().getSubtargetInfo());
+ OutStreamer->emitLabel(LblSym);
+ emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal);
+ }
+ }
+}
+
/// EmitConstantPool - Print to the current output stream assembly
/// representations of the constants in the constant pool MCP. This is
/// used to print out constants which have been "spilled to memory" by
@@ -82,32 +173,7 @@ void XtensaAsmPrinter::emitConstantPool() {
}
}
- if (CPE.isMachineConstantPoolEntry()) {
- report_fatal_error("This constantpool type is not supported yet");
- } else {
- MCSymbol *LblSym = GetCPISymbol(i);
- // TODO find a better way to check whether we emit data to .s file
- if (OutStreamer->hasRawTextSupport()) {
- std::string str("\t.literal ");
- str += LblSym->getName();
- str += ", ";
- const Constant *C = CPE.Val.ConstVal;
-
- if (const auto *CFP = dyn_cast<ConstantFP>(C)) {
- str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true);
- } else if (const auto *CI = dyn_cast<ConstantInt>(C)) {
- str += toString(CI->getValue(), 10, true);
- } else {
- report_fatal_error(
- "This constant type is not supported yet in constantpool");
- }
-
- OutStreamer->emitRawText(StringRef(str));
- } else {
- OutStreamer->emitLabel(LblSym);
- emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal);
- }
- }
+ emitMachineConstantPoolEntry(CPE, i);
}
}
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
index d9b8e8ed2b64ba6..c59f2b6b9ece953 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -17,6 +17,7 @@
#include "XtensaTargetMachine.h"
#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/Support/Compiler.h"
namespace llvm {
@@ -37,6 +38,8 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter {
StringRef getPassName() const override { return "Xtensa Assembly Printer"; }
void emitInstruction(const MachineInstr *MI) override;
void emitConstantPool() override;
+ void emitMachineConstantPoolEntry(const MachineConstantPoolEntry &CPE, int i);
+ void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 6e8951591d3e794..acf0cdaff731b67 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -13,6 +13,7 @@
//
//===----------------------------------------------------------------------===//
+#include "XtensaConstantPoolValue.h"
#include "XtensaISelLowering.h"
#include "XtensaSubtarget.h"
#include "XtensaTargetMachine.h"
@@ -49,6 +50,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
setOperationAction(ISD::Constant, MVT::i32, Custom);
setOperationAction(ISD::Constant, MVT::i64, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
// No sign extend instructions for i1
for (MVT VT : MVT::integer_valuetypes()) {
@@ -58,11 +61,17 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
}
setOperationAction(ISD::ConstantPool, PtrVT, Custom);
+ setOperationAction(ISD::BlockAddress, PtrVT, Custom);
// Compute derived properties from the register classes
computeRegisterProperties(STI.getRegisterInfo());
}
+bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool ForCodeSize) const {
+ return false;
+}
+
//===----------------------------------------------------------------------===//
// Calling conventions
//===----------------------------------------------------------------------===//
@@ -343,6 +352,31 @@ SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
return Op;
}
+SDValue XtensaTargetLowering::LowerImmediateFP(SDValue Op, SelectionDAG & DAG)
+ const {
+ if (Op.getValueType() != MVT::f32)
+ return Op;
+ const ConstantFPSDNode *CN = cast<ConstantFPSDNode>(Op);
+ SDLoc DL(CN);
+ APFloat apval = CN->getValueAPF();
+ int64_t value = llvm::bit_cast<uint32_t>(apval.convertToFloat());
+ Type *Ty = Type::getInt32Ty(*DAG.getContext());
+ Constant *CV = ConstantInt::get(Ty, value);
+ SDValue CP = DAG.getConstantPool(CV, MVT::i32);
+ return DAG.getNode(ISD::BITCAST, DL, MVT::f32, CP);
+}
+
+SDValue XtensaTargetLowering::LowerBlockAddress(BlockAddressSDNode *Node,
+ SelectionDAG &DAG) const {
+ const BlockAddress *BA = Node->getBlockAddress();
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
+ XtensaConstantPoolValue *CPV =
+ XtensaConstantPoolConstant::Create(BA, 0, XtensaCP::CPBlockAddress);
+ SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
+ SDValue CPWrap = getAddrPCRel(CPAddr, DAG);
+ return CPWrap;
+}
+
SDValue XtensaTargetLowering::getAddrPCRel(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
@@ -354,11 +388,13 @@ SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP,
SelectionDAG &DAG) const {
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDValue Result;
- if (!CP->isMachineConstantPoolEntry()) {
+
+ if (CP->isMachineConstantPoolEntry()) {
+ Result =
+ DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
+ } else {
Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),
CP->getOffset());
- } else {
- report_fatal_error("This constantpool type is not supported yet");
}
return getAddrPCRel(Result, DAG);
@@ -369,6 +405,10 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
switch (Op.getOpcode()) {
case ISD::Constant:
return LowerImmediate(Op, DAG);
+ case ISD::ConstantFP:
+ return LowerImmediateFP(Op, DAG);
+ case ISD::BlockAddress:
+ return LowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
case ISD::ConstantPool:
return LowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
default:
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index 79a48ace444f1ac..af85420e07bf0ab 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -38,6 +38,8 @@ class XtensaTargetLowering : public TargetLowering {
explicit XtensaTargetLowering(const TargetMachine &TM,
const XtensaSubtarget &STI);
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool ForCodeSize) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
@@ -60,6 +62,8 @@ class XtensaTargetLowering : public TargetLowering {
const XtensaSubtarget &Subtarget;
SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerBlockAddress(BlockAddressSDNode *Node, SelectionDAG &DAG) const;
SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
index b7a7c02ac2b5e78..ba5a426c269e284 100644
--- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
@@ -42,6 +42,13 @@ XtensaMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None;
switch (MOTy) {
+ case MachineOperand::MO_MachineBasicBlock:
+ Symbol = MO.getMBB()->getSymbol();
+ break;
+ case MachineOperand::MO_BlockAddress:
+ Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress());
+ Offset += MO.getOffset();
+ break;
case MachineOperand::MO_ConstantPoolIndex:
Symbol = GetConstantPoolIndexSymbol(MO);
Offset += MO.getOffset();
@@ -79,6 +86,8 @@ MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
return MCOperand::createImm(MO.getImm() + Offset);
case MachineOperand::MO_RegisterMask:
break;
+ case MachineOperand::MO_MachineBasicBlock:
+ case MachineOperand::MO_BlockAddress:
case MachineOperand::MO_ConstantPoolIndex:
return LowerSymbolOperand(MO, MOTy, Offset);
default:
diff --git a/llvm/test/CodeGen/Xtensa/constantpool.ll b/llvm/test/CodeGen/Xtensa/constantpool.ll
index 9b380d2c37b9e00..5019c75eb683292 100644
--- a/llvm/test/CodeGen/Xtensa/constantpool.ll
+++ b/llvm/test/CodeGen/Xtensa/constantpool.ll
@@ -26,3 +26,55 @@ define dso_local i64 @const_int64() #0 {
%2 = load i64, ptr %1, align 8
ret i64 %2
}
+
+define dso_local float @const_fp() #0 {
+; CHECK: .literal_position
+; CHECK-NEXT: .literal .LCPI2_0, 1092721050
+; CHECK-LABEL: const_fp:
+; CHECK: l32r a2, .LCPI2_0
+ %1 = alloca float, align 4
+ store float 0x4024333340000000, ptr %1, align 4
+ %2 = load float, ptr %1, align 4
+ ret float %2
+}
+
+define dso_local i64 @const_double() #0 {
+; CHECK: .literal_position
+; CHECK-NEXT: .literal .LCPI3_0, 1070945621
+; CHECK-NEXT: .literal .LCPI3_1, 1371607770
+; CHECK-LABEL: const_double:
+; CHECK: l32r a3, .LCPI3_0
+; CHECK: l32r a2, .LCPI3_1
+ %1 = alloca double, align 8
+ %2 = alloca double, align 8
+ store double 0x3FD5555551C112DA, ptr %2, align 8
+ %3 = load double, ptr %2, align 8
+ store double %3, ptr %1, align 8
+ %4 = load i64, ptr %1, align 8
+ ret i64 %4
+}
+
+; Test placement of the block address in constantpool
+
+define dso_local i32 @const_blockaddress(i32 noundef %0) #0 {
+; CHECK: .literal_position
+; CHECK-NEXT: .literal .LCPI4_0, .Ltmp0
+; CHECK-LABEL: const_blockaddress:
+; CHECK: l32r a8, .LCPI4_0
+; CHECK: jx a8
+; CHECK-NEXT: .Ltmp0:
+ %2 = alloca i32, align 4
+ %3 = alloca ptr, align 4
+ store i32 %0, ptr %2, align 4
+ store ptr blockaddress(@const_blockaddress, %5), ptr %3, align 4
+ %4 = load ptr, ptr %3, align 4
+ br label %7
+
+5: ; preds = %7
+ %6 = load i32, ptr %2, align 4
+ ret i32 %6
+
+7: ; preds = %1
+ %8 = phi ptr [ %4, %1 ]
+ indirectbr ptr %8, [label %5]
+}
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