[llvm] AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (PR #78482)

[Matt Arsenault via llvm-commits]

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@@ -210,6 +210,14 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
 bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
   const Register DefReg = I.getOperand(0).getReg();
   const LLT DefTy = MRI->getType(DefReg);
+  // Lane mask PHIs, PHI where all register operands have sgpr register class
+  // with S1 LLT, are already selected in divergence lowering pass.
+  if (I.getOpcode() == AMDGPU::PHI) {
+    assert(MRI->getType(DefReg) == LLT::scalar(1));
+    assert(TRI.isSGPRClass(MRI->getRegClass(DefReg)));
+    return true;
+  }
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arsenm wrote:

Remove this, we shouldn't be trying to select any PHI as-is. You should instead remove the special case isPHI handling in ::select and just make it a regular switch case over G_PHI 

https://github.com/llvm/llvm-project/pull/78482