[llvm] [X86][MC] Fix wrong encoding of promoted BMI instructions due to missing NoCD8 (PR #78386)

[via llvm-commits]

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@@ -1375,39 +1375,32 @@ let Predicates = [HasBMI2, NoTBM, HasEGPR] in {
                              (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
 }
 
-multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
-                         X86MemOperand x86memop, SDPatternOperator OpNode,
-                         PatFrag ld_frag, string Suffix = ""> {
-  def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
-                    !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
-                  NoCD8, VVVV, Sched<[WriteALU]>;
-  def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
-                    !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
-                  NoCD8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
+multiclass bmi_pdep_pext<string mnemonic, X86TypeInfo t, SDPatternOperator OpNode,
+                         string suffix = ""> {
+  def rr#suffix : ITy<0xF5, MRMSrcReg, t, (outs t.RegClass:$dst),
+                      (ins t.RegClass:$src1, t.RegClass:$src2),
+                      mnemonic, binop_ndd_args,
+                      [(set t.RegClass:$dst, (OpNode t.RegClass:$src1, t.RegClass:$src2))]>,
+                  VVVV, Sched<[WriteALU]>;
+  def rm#suffix : ITy<0xF5, MRMSrcMem, t, (outs t.RegClass:$dst),
+                      (ins t.RegClass:$src1, t.MemOperand:$src2),
+                      mnemonic, binop_ndd_args,
+                      [(set t.RegClass:$dst, (OpNode t.RegClass:$src1, (t.LoadNode addr:$src2)))]>,
+                  VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
 }
 
 let Predicates = [HasBMI2, NoEGPR] in {
-  defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
-                               X86pdep, loadi32>, T8, XD, VEX;
-  defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
-                               X86pdep, loadi64>, T8, XD, REX_W, VEX;
-  defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
-                               X86pext, loadi32>, T8, XS, VEX;
-  defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
-                               X86pext, loadi64>, T8, XS, REX_W, VEX;
+  defm PDEP32 : bmi_pdep_pext<"pdep", Xi32, X86pdep>, T8, XD, VEX;
+  defm PDEP64 : bmi_pdep_pext<"pdep", Xi64, X86pdep>, T8, XD, REX_W, VEX;
+  defm PEXT32 : bmi_pdep_pext<"pext", Xi32, X86pext>, T8, XS, VEX;
+  defm PEXT64 : bmi_pdep_pext<"pext", Xi64, X86pext>, T8, XS, REX_W, VEX;
 }
 
 let Predicates = [HasBMI2, HasEGPR] in {
-  defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
-                               X86pdep, loadi32, "_EVEX">, T8, XD, EVEX;
-  defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
-                               X86pdep, loadi64, "_EVEX">, T8, XD, REX_W, EVEX;
-  defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
-                               X86pext, loadi32, "_EVEX">, T8, XS, EVEX;
-  defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
-                               X86pext, loadi64, "_EVEX">, T8, XS, REX_W, EVEX;
+  defm PDEP32 : bmi_pdep_pext<"pdep", Xi32, X86pdep, "_EVEX">, T8, XD, EVEX;
+  defm PDEP64 : bmi_pdep_pext<"pdep", Xi64, X86pdep, "_EVEX">, T8, XD, REX_W, EVEX;
+  defm PEXT32 : bmi_pdep_pext<"pext", Xi32, X86pext, "_EVEX">, T8, XS, EVEX;
+  defm PEXT64 : bmi_pdep_pext<"pext", Xi64, X86pext, "_EVEX">, T8, XS, REX_W, EVEX;
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XinWang10 wrote:

Maybe just T8?

https://github.com/llvm/llvm-project/pull/78386