[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension. (PR #76785)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 17 18:30:33 PST 2024

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/76785

Previous message: [llvm] ba81477 - Recommit "[RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension." (#76785)
Next message: [llvm] [llvm-lib][Object][COFF] Use ARM64 machine type for import library descriptor objects. (PR #78537)
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