[llvm] [RISCV][ISel] Remove redundant vmerge for the vwadd. (PR #78403)

[via llvm-commits]

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@@ -13457,6 +13457,55 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   return InputRootReplacement;
 }
 
+// (vwadd y, (select cond, x, 0)) -> select cond (vwadd y, x), y
+static SDValue combineVWADDSelect(SDNode *N, SelectionDAG &DAG) {
+  unsigned Opc = N->getOpcode();
+  assert(Opc == RISCVISD::VWADD_VL || Opc == RISCVISD::VWADD_W_VL ||
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sun-jacobi wrote:

The check in `performVWADD_VLCombine` is for  `RISCVISD::VWADD_W_VL` and `RISCVISD::VWADDU_W_VL`. 
We need to first do `combineBinOp_VLToVWBinOp_VL` on those.

https://github.com/llvm/llvm-project/pull/78403