[llvm] [RISCV][ISel] Remove redundant vmerge for the vwadd. (PR #78403)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 16:19:56 PST 2024
================
@@ -13457,6 +13457,55 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
return InputRootReplacement;
}
+// (vwadd y, (select cond, x, 0)) -> select cond (vwadd y, x), y
+static SDValue combineVWADDSelect(SDNode *N, SelectionDAG &DAG) {
+ unsigned Opc = N->getOpcode();
+ assert(Opc == RISCVISD::VWADD_VL || Opc == RISCVISD::VWADD_W_VL ||
----------------
topperc wrote:
It can't be VWADD_VL due to the check in `performVWADD_VLCombine` right?
https://github.com/llvm/llvm-project/pull/78403
More information about the llvm-commits
mailing list