[llvm] f2b5a31 - [RISCV] Add LUI/AUIPC+ADDI fusions to sifive-p450. (#78501)

[via llvm-commits]

Author: Craig Topper
Date: 2024-01-17T16:01:34-08:00
New Revision: f2b5a314b29275f2092af3ec26f42272daa4312c

URL: https://github.com/llvm/llvm-project/commit/f2b5a314b29275f2092af3ec26f42272daa4312c
DIFF: https://github.com/llvm/llvm-project/commit/f2b5a314b29275f2092af3ec26f42272daa4312c.diff

LOG: [RISCV] Add LUI/AUIPC+ADDI fusions to sifive-p450. (#78501)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 722f867f9592f5..d1cd9ba1dd84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -233,7 +233,9 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
                                        FeatureStdExtZbb,
                                        FeatureStdExtZbs,
                                        FeatureStdExtZfhmin],
-                                      [TuneConditionalCompressedMoveFusion]>;
+                                      [TuneConditionalCompressedMoveFusion,
+                                       TuneLUIADDIFusion,
+                                       TuneAUIPCADDIFusion]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,