[llvm] bc90b91 - Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2024-01-17T19:27:36Z
New Revision: bc90b91885263eb2128315ff636b7f2d200eab48

URL: https://github.com/llvm/llvm-project/commit/bc90b91885263eb2128315ff636b7f2d200eab48
DIFF: https://github.com/llvm/llvm-project/commit/bc90b91885263eb2128315ff636b7f2d200eab48.diff

LOG: Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"

This reverts commit 4b7d997aaed7a2399d5e73fc3adfaaa6a3d35d1f.

A miscompile was reported
<https://github.com/llvm/llvm-project/pull/77610#issuecomment-1896193835>.
Reverting so it can be investigated.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.h
    llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 857e8979762cdc..9813c7a70dfc31 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1580,12 +1580,6 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default:
     break;
-  case RISCV::ADD:
-    if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0)
-      return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
-    if (MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0)
-      return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
-    break;
   case RISCV::ADDI:
     // Operand 1 can be a frameindex but callers expect registers
     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
@@ -2561,33 +2555,6 @@ std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
   return std::nullopt;
 }
 
-bool RISCVInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
-                                             const Register Reg,
-                                             int64_t &ImmVal) const {
-  // Handle moves of X0.
-  if (auto DestSrc = isCopyInstr(MI)) {
-    if (DestSrc->Source->getReg() != RISCV::X0)
-      return false;
-    const Register DstReg = DestSrc->Destination->getReg();
-    if (DstReg != Reg)
-      return false;
-    ImmVal = 0;
-    return true;
-  }
-
-  if (!(MI.getOpcode() == RISCV::ADDI || MI.getOpcode() == RISCV::ADDIW ||
-        MI.getOpcode() == RISCV::ORI))
-    return false;
-  if (MI.getOperand(0).getReg() != Reg)
-    return false;
-  if (!MI.getOperand(1).isReg() || MI.getOperand(1).getReg() != RISCV::X0)
-    return false;
-  if (!MI.getOperand(2).isImm())
-    return false;
-  ImmVal = MI.getOperand(2).getImm();
-  return true;
-}
-
 // MIR printer helper function to annotate Operands with a comment.
 std::string RISCVInstrInfo::createMIROperandComment(
     const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 84015a66fb23a4..7e1d3f31180650 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -212,9 +212,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                            Register Reg) const override;
 
-  bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
-                               int64_t &ImmVal) const override;
-
   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
                              unsigned &SrcOpIdx2) const override;
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,

diff  --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 4b1754cd4fcdcf..5836239bc56fd6 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -94,52 +94,6 @@ TEST_P(RISCVInstrInfoTest, IsAddImmediate) {
   }
 }
 
-TEST_P(RISCVInstrInfoTest, GetConstValDefinedInReg) {
-  const RISCVInstrInfo *TII = ST->getInstrInfo();
-  DebugLoc DL;
-  int64_t ImmVal;
-
-  auto *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
-                  .addReg(RISCV::X2)
-                  .addReg(RISCV::X3)
-                  .getInstr();
-  EXPECT_FALSE(TII->getConstValDefinedInReg(*MI1, RISCV::X1, ImmVal));
-
-  auto *MI2 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1)
-                  .addReg(RISCV::X0)
-                  .addImm(-128)
-                  .getInstr();
-  EXPECT_FALSE(TII->getConstValDefinedInReg(*MI2, RISCV::X0, ImmVal));
-  ASSERT_TRUE(TII->getConstValDefinedInReg(*MI2, RISCV::X1, ImmVal));
-  EXPECT_EQ(ImmVal, -128);
-
-  auto *MI3 = BuildMI(*MF, DL, TII->get(RISCV::ORI), RISCV::X2)
-                  .addReg(RISCV::X0)
-                  .addImm(1024)
-                  .getInstr();
-  EXPECT_FALSE(TII->getConstValDefinedInReg(*MI3, RISCV::X0, ImmVal));
-  ASSERT_TRUE(TII->getConstValDefinedInReg(*MI3, RISCV::X2, ImmVal));
-  EXPECT_EQ(ImmVal, 1024);
-
-  if (ST->is64Bit()) {
-    auto *MI4 = BuildMI(*MF, DL, TII->get(RISCV::ADDIW), RISCV::X2)
-                    .addReg(RISCV::X0)
-                    .addImm(512)
-                    .getInstr();
-    EXPECT_FALSE(TII->getConstValDefinedInReg(*MI4, RISCV::X0, ImmVal));
-    ASSERT_TRUE(TII->getConstValDefinedInReg(*MI4, RISCV::X2, ImmVal));
-    EXPECT_EQ(ImmVal, 512);
-  }
-
-  auto *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
-                  .addReg(RISCV::X0)
-                  .addReg(RISCV::X0)
-                  .getInstr();
-  EXPECT_FALSE(TII->getConstValDefinedInReg(*MI5, RISCV::X0, ImmVal));
-  ASSERT_TRUE(TII->getConstValDefinedInReg(*MI5, RISCV::X1, ImmVal));
-  EXPECT_EQ(ImmVal, 0);
-}
-
 TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
   const RISCVInstrInfo *TII = ST->getInstrInfo();
   const TargetRegisterInfo *TRI = ST->getRegisterInfo();