[llvm] [PowerPC] lower partial vector store cost (PR #78358)

[via llvm-commits]

https://github.com/RolandF77 updated https://github.com/llvm/llvm-project/pull/78358

>From 326febca1d85d1719e9b3061c5f380f0174316cf Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Tue, 16 Jan 2024 22:07:04 +0000
Subject: [PATCH 1/2] lower partial vector store cost

---
 .../Target/PowerPC/PPCTargetTransformInfo.cpp |  5 +++--
 .../Analysis/CostModel/PowerPC/load_store.ll  | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 062b53e24a0d79..eb578c59f57080 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -788,9 +788,10 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   // VSX has 32b/64b load instructions. Legalization can handle loading of
   // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
   // PPCTargetLowering can't compute the cost appropriately. So here we
-  // explicitly check this case.
+  // explicitly check this case. There are also corresponding store 
+  // instructions.
   unsigned MemBytes = Src->getPrimitiveSizeInBits();
-  if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
+  if (ST->hasVSX() && IsAltivecType &&
       (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
     return 1;
 
diff --git a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll
index 574a3d40d27344..167cdf9c333036 100644
--- a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll
+++ b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll
@@ -43,3 +43,22 @@ define i32 @loads(i32 %arg) {
   ret i32 undef
 }
 
+define i32 @partialvector32(i32 %arg) #0 {
+
+  ; CHECK: cost of 1 {{.*}} store
+  store <4 x i8> undef, ptr undef, align 16
+
+  ret i32 undef
+}
+
+define i32 @partialvector64(i32 %arg) #1 {
+
+  ; CHECK: cost of 1 {{.*}} store
+  store <4 x i16> undef, ptr undef, align 16
+
+  ret i32 undef
+}
+
+attributes #0 = { "target-features"="+power8-vector,+vsx" }
+
+attributes #1 = { "target-features"="+vsx" }

>From be071dda8fc001ea5e2c8e29a654cdc3b66d8fa1 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Wed, 17 Jan 2024 19:09:13 +0000
Subject: [PATCH 2/2] formatting

---
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index eb578c59f57080..958353f2b4f6f8 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -788,7 +788,7 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   // VSX has 32b/64b load instructions. Legalization can handle loading of
   // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
   // PPCTargetLowering can't compute the cost appropriately. So here we
-  // explicitly check this case. There are also corresponding store 
+  // explicitly check this case. There are also corresponding store
   // instructions.
   unsigned MemBytes = Src->getPrimitiveSizeInBits();
   if (ST->hasVSX() && IsAltivecType &&