[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

Jun Wang via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 17 11:09:37 PST 2024


================
@@ -29,6 +29,39 @@
 
 using namespace llvm;
 
+static bool CC_AMDGPU_Custom_I1(unsigned ValNo, MVT ValVT, MVT LocVT,
+                                CCValAssign::LocInfo LocInfo,
+                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
+  static bool IsWave64 = static_cast<const GCNSubtarget &>(
+                             State.getMachineFunction().getSubtarget())
+                             .isWave64();
+
+  static const MCPhysReg I1RegList1[] = {
+      AMDGPU::SGPR0_SGPR1,   AMDGPU::SGPR2_SGPR3,   AMDGPU::SGPR4_SGPR5,
----------------
jwanggit86 wrote:

This issue deals with i1 arg/return only. Inreg args are handled separately. If you are thinking about a mixed case as follows:
```
foo (i32 inreg %arg0, i1 %arg1)
```
Currently for gfx900,  %arg0 is assigned to s4, and %arg1 to s[6:7]. If in this case you want %arg1 to be given s[5:6], I suppose the list of registers can be changed from `{ ... sgpr4_sgpr5, sgpr6_sgpr7, ...}` to `{... sgpr4_sgpr5, sgpr5_sgrp6, sgpr6_sgrp7, ...}`.
Is this what you had in mind?

https://github.com/llvm/llvm-project/pull/72461


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