[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -2753,6 +2758,16 @@ struct RegPairInfo {
 
 } // end anonymous namespace
 
+unsigned findFreePredicateAsCounterReg(MachineFunction &MF) {
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momchil-velikov wrote:

This function does not do what it needs to do. A "reserved" register (`isReserved`) means the register is not available to the register allocator, which currently is always true for all the predicate registers.
What we need here is an available register, i.e. a register that does not already contain a useful value.

https://github.com/llvm/llvm-project/pull/77665