[llvm] [RISCV] Add IntrArgMemOnly for vector load/store intrinsic (PR #78415)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 01:52:53 PST 2024
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@@ -177,7 +179,8 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem]>,
+ [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem,
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wangpc-pp wrote:
fault-only-first load may write vl, is this still `IntrArgMemOnly`?
https://github.com/llvm/llvm-project/pull/78415
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