[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Matt Arsenault via llvm-commits]

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@@ -2831,8 +2831,13 @@ SDValue SITargetLowering::LowerFormalArguments(
       RC = &AMDGPU::VGPR_32RegClass;
     else if (AMDGPU::SGPR_32RegClass.contains(Reg))
       RC = &AMDGPU::SGPR_32RegClass;
-    else
-      llvm_unreachable("Unexpected register class in LowerFormalArguments!");
+    else {
+      if (VT == MVT::i1 && Subtarget->isWave64())
----------------
arsenm wrote:

To operate within the constraints of SILowerI1Copies, we might need to find a way to get this broken into:

```
  %3:sreg_64_xexec = COPY $sgpr0_sgpr1
  %4:vreg_1 = COPY %3
  %5:sreg_64_xexec = COPY %4

```

https://github.com/llvm/llvm-project/pull/72461