[llvm] [RISCV][ISel] Add ISel support for experimental Zimop extension (PR #77089)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 00:05:48 PST 2024
================
@@ -8404,6 +8404,83 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
+ case Intrinsic::riscv_mopr: {
+ unsigned mopr_id = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+ switch (mopr_id) {
+#define RISCV_MOPR_64_CASE(MOPR_ID, OPCODE) \
+ case MOPR_ID: { \
+ if (RV64LegalI32 && Subtarget.is64Bit() && \
+ Op.getValueType() == MVT::i32) { \
+ SDValue NewOp = \
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1)); \
+ SDValue Res = DAG.getNode(OPCODE, DL, MVT::i64, NewOp); \
+ return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res); \
+ } \
+ return DAG.getNode(OPCODE, DL, XLenVT, Op.getOperand(1)); \
+ }
+ RISCV_MOPR_64_CASE(0, RISCVISD::MOPR0)
----------------
ln8-8 wrote:
I have tried to change it as you asked. Unfortunately, I had some trouble with it. I am not very competent in tblgen syntax and could not get corresponding instruction which depends on the third operand. If you can give an example it will be nice.
https://github.com/llvm/llvm-project/pull/77089
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