[llvm] [X86][APX] Avoid generating illegal MI_ND ndd instructions (PR #78233)

[Shengchen Kan via llvm-commits]

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@@ -940,8 +940,8 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
     def 32mi8_ND  : BinOpMI8F_RF<mnemonic, Xi32, MemMRM>;
     def 64mi8_ND  : BinOpMI8F_RF<mnemonic, Xi64, MemMRM>;
     def 16mi_ND   : BinOpMIF_RF<0x81, mnemonic, Xi16, opnode, MemMRM>, PD;
-    def 32mi_ND   : BinOpMIF_RF<0x81, mnemonic, Xi32, opnode, MemMRM>;
-    def 64mi32_ND : BinOpMIF_RF<0x81, mnemonic, Xi64, opnode, MemMRM>;
+    def 32mi_ND   : BinOpMIF_RF<0x81, mnemonic, Xi32, opnode, MemMRM, nosegaddr>;
+    def 64mi32_ND : BinOpMIF_RF<0x81, mnemonic, Xi64, opnode, MemMRM, nosegaddr>;
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KanRobert wrote:

Currently, we always select mi variant and compress it to mi8  if possible.  This implementation prevents mi32_ND being used for segment address even when the immediate is 8-bit. Namely, mi8_ND can not be used for segment address either, which does not make sense.

https://github.com/llvm/llvm-project/pull/78233