[llvm] [RISCV] Support isel for Zacas for 2*XLen types. (PR #77814)

[James Y Knight via llvm-commits]

jyknight wrote:

This change isn't OK - we shouldn't add any new expansions of Load to CmpXChg. Unless there is an atomic 128-bit load operation also available in RISC-V, we cannot use amocas.q for implementing atomics.

We made the mistake of expanding load to cmpxchg on X86 and AArch64, but it's wrong. An atomic load 
should work on read-only memory, and expanding to cmpxchg does not. Furthermore, turning memory reads into writes is extremely bad for scalability.

Luckily, on newer X86 and AArch64 microarchitectures there is support for 128-bit atomic load/store, so we can DTRT on newer microarchitectures.

GCC fixed this partially on X86: the generated code always defers to libatomic unless the 128-bit atomic load/store is available, but libatomic still has the broken behavior, for compatibility with older generated code. I believe they avoided making the mistake on AArch64. (See #75081).

https://github.com/llvm/llvm-project/pull/77814