[llvm] 662d1cb - [X86] Add test case for Issue #78109

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 16 08:33:37 PST 2024


Author: Simon Pilgrim
Date: 2024-01-16T16:33:21Z
New Revision: 662d1cb86bc156f4c8b5d991b3262e3649479540

URL: https://github.com/llvm/llvm-project/commit/662d1cb86bc156f4c8b5d991b3262e3649479540
DIFF: https://github.com/llvm/llvm-project/commit/662d1cb86bc156f4c8b5d991b3262e3649479540.diff

LOG: [X86] Add test case for Issue #78109

Added: 
    llvm/test/CodeGen/X86/pr78109.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/pr78109.ll b/llvm/test/CodeGen/X86/pr78109.ll
new file mode 100644
index 00000000000000..f152294c1b8d8e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr78109.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
+
+; FIXME: Failure to recognise undef elements in constant foldable splats
+define <4 x i32> @PR78109() {
+; SSE-LABEL: PR78109:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movaps {{.*#+}} xmm0 = [1,1,1,1]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR78109:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]
+; AVX-NEXT:    retq
+  %shuffle.1 = shufflevector <4 x i32> <i32 7, i32 7, i32 0, i32 7>, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 2, i32 1, i32 1> ; <0, 0, 7, 7>
+  %shift = lshr <4 x i32> %shuffle.1, <i32 0, i32 0, i32 1, i32 0> ; <0, 0, 3, 7>
+  %shuffle.2 = shufflevector <4 x i32> %shift, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 2, i32 0, i32 0> ; <3, 3, 0, 0>
+  %shuffle.3 = shufflevector <4 x i32> %shuffle.2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <0, 1, 0, 1>
+  ret <4 x i32> %shuffle.3
+}


        


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