[llvm] dfaf09b - [X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrShiftRotate.td

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-16T23:02:02+08:00
New Revision: dfaf09b5d1a0da1a700808d35a12a2a15f38f4ab

URL: https://github.com/llvm/llvm-project/commit/dfaf09b5d1a0da1a700808d35a12a2a15f38f4ab
DIFF: https://github.com/llvm/llvm-project/commit/dfaf09b5d1a0da1a700808d35a12a2a15f38f4ab.diff

LOG: [X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrShiftRotate.td

This patch is to extract NFC in #77433 into a separate commit.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrShiftRotate.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index a87af5c680e18c..dbfd66ae489dda 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -284,7 +284,7 @@ defm SHRX64: ShiftX<"shrx", Xi64>, XD;
 defm SHLX32: ShiftX<"shlx", Xi32>, PD;
 defm SHLX64: ShiftX<"shlx", Xi64>, PD;
 
-let Predicates = [HasBMI2] in {
+multiclass RORX_Pats {
   // Prefer RORX which is non-destructive and doesn't update EFLAGS.
   let AddedComplexity = 10 in {
     def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
@@ -307,7 +307,9 @@ let Predicates = [HasBMI2] in {
             (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
   def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
             (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
+}
 
+multiclass ShiftX_Pats<SDNode op> {
   // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
   // immediate shift, i.e. the following code is considered better
   //
@@ -322,34 +324,13 @@ let Predicates = [HasBMI2] in {
   //  ... %edi, ...
   //
   let AddedComplexity = 1 in {
-    def : Pat<(sra GR32:$src1, GR8:$src2),
-              (SARX32rr GR32:$src1,
-                        (INSERT_SUBREG
-                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-    def : Pat<(sra GR64:$src1, GR8:$src2),
-              (SARX64rr GR64:$src1,
-                        (INSERT_SUBREG
-                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-
-    def : Pat<(srl GR32:$src1, GR8:$src2),
-              (SHRX32rr GR32:$src1,
-                        (INSERT_SUBREG
-                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-    def : Pat<(srl GR64:$src1, GR8:$src2),
-              (SHRX64rr GR64:$src1,
-                        (INSERT_SUBREG
-                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-
-    def : Pat<(shl GR32:$src1, GR8:$src2),
-              (SHLX32rr GR32:$src1,
-                        (INSERT_SUBREG
-                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-    def : Pat<(shl GR64:$src1, GR8:$src2),
-              (SHLX64rr GR64:$src1,
-                        (INSERT_SUBREG
-                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
+   def : Pat<(op GR32:$src1, GR8:$src2),
+              (!cast<Instruction>(NAME#"32rr") GR32:$src1,
+               (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
+   def : Pat<(op GR64:$src1, GR8:$src2),
+              (!cast<Instruction>(NAME#"64rr") GR64:$src1,
+               (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
   }
-
   // We prefer to use
   //  mov (%ecx), %esi
   //  shl $imm, $esi
@@ -360,30 +341,17 @@ let Predicates = [HasBMI2] in {
   //  shlx %al, (%ecx), %esi
   //
   // This priority is enforced by IsProfitableToFoldLoad.
-  def : Pat<(sra (loadi32 addr:$src1), GR8:$src2),
-            (SARX32rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-  def : Pat<(sra (loadi64 addr:$src1), GR8:$src2),
-            (SARX64rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-
-  def : Pat<(srl (loadi32 addr:$src1), GR8:$src2),
-            (SHRX32rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-  def : Pat<(srl (loadi64 addr:$src1), GR8:$src2),
-            (SHRX64rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-
-  def : Pat<(shl (loadi32 addr:$src1), GR8:$src2),
-            (SHLX32rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
-  def : Pat<(shl (loadi64 addr:$src1), GR8:$src2),
-            (SHLX64rm addr:$src1,
-                      (INSERT_SUBREG
-                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
+  def : Pat<(op (loadi32 addr:$src1), GR8:$src2),
+             (!cast<Instruction>(NAME#"32rm") addr:$src1,
+              (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
+  def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
+             (!cast<Instruction>(NAME#"64rm") addr:$src1,
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
+}
+
+let Predicates = [HasBMI2] in {
+  defm : RORX_Pats;
+  defm SARX : ShiftX_Pats<sra>;
+  defm SHRX : ShiftX_Pats<srl>;
+  defm SHLX : ShiftX_Pats<shl>;
 }