[llvm] b1eaffd - [X86][test] Add test for lowering NDD AND
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 16 04:14:59 PST 2024
Author: Shengchen Kan
Date: 2024-01-16T20:09:40+08:00
New Revision: b1eaffd389045827a649b95726824bfc5d0de0fd
URL: https://github.com/llvm/llvm-project/commit/b1eaffd389045827a649b95726824bfc5d0de0fd
DIFF: https://github.com/llvm/llvm-project/commit/b1eaffd389045827a649b95726824bfc5d0de0fd.diff
LOG: [X86][test] Add test for lowering NDD AND
We supported encoding/decoding for APX AND in #76319
This test should be added in #77564 but was missing.
Added:
llvm/test/CodeGen/X86/apx/and.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
new file mode 100644
index 00000000000000..1f7b694e6c67b4
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -0,0 +1,595 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s
+
+define i8 @and8rr(i8 noundef %a, i8 noundef %b) {
+; CHECK-LABEL: and8rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i8 %a, %b
+ ret i8 %and
+}
+
+define i16 @and16rr(i16 noundef %a, i16 noundef %b) {
+; CHECK-LABEL: and16rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, %b
+ ret i16 %and
+}
+
+define i32 @and32rr(i32 noundef %a, i32 noundef %b) {
+; CHECK-LABEL: and32rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, %b
+ ret i32 %and
+}
+
+define i64 @and64rr(i64 noundef %a, i64 noundef %b) {
+; CHECK-LABEL: and64rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, %rdi, %rax
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, %b
+ ret i64 %and
+}
+
+define i8 @and8rm(i8 noundef %a, ptr %b) {
+; CHECK-LABEL: and8rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb (%rsi), %dil, %al
+; CHECK-NEXT: retq
+entry:
+ %t = load i8, ptr %b
+ %and = and i8 %a, %t
+ ret i8 %and
+}
+
+define i16 @and16rm(i16 noundef %a, ptr %b) {
+; CHECK-LABEL: and16rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw (%rsi), %di, %ax
+; CHECK-NEXT: retq
+entry:
+ %t = load i16, ptr %b
+ %and = and i16 %a, %t
+ ret i16 %and
+}
+
+define i32 @and32rm(i32 noundef %a, ptr %b) {
+; CHECK-LABEL: and32rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl (%rsi), %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %t = load i32, ptr %b
+ %and = and i32 %a, %t
+ ret i32 %and
+}
+
+define i64 @and64rm(i64 noundef %a, ptr %b) {
+; CHECK-LABEL: and64rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq (%rsi), %rdi, %rax
+; CHECK-NEXT: retq
+entry:
+ %t = load i64, ptr %b
+ %and = and i64 %a, %t
+ ret i64 %and
+}
+
+define i16 @and16ri8(i16 noundef %a) {
+; CHECK-LABEL: and16ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, 123
+ ret i16 %and
+}
+
+define i32 @and32ri8(i32 noundef %a) {
+; CHECK-LABEL: and32ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, 123
+ ret i32 %and
+}
+
+define i64 @and64ri8(i64 noundef %a) {
+; CHECK-LABEL: and64ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, 123
+ ret i64 %and
+}
+
+define i8 @and8ri(i8 noundef %a) {
+; CHECK-LABEL: and8ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, %dil, %al
+; CHECK-NEXT: retq
+entry:
+ %and = and i8 %a, 123
+ ret i8 %and
+}
+
+define i16 @and16ri(i16 noundef %a) {
+; CHECK-LABEL: and16ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $1234, %edi, %eax # imm = 0x4D2
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, 1234
+ ret i16 %and
+}
+
+define i32 @and32ri(i32 noundef %a) {
+; CHECK-LABEL: and32ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, 123456
+ ret i32 %and
+}
+
+define i64 @and64ri(i64 noundef %a) {
+; CHECK-LABEL: and64ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, 123456
+ ret i64 %and
+}
+
+define i8 @and8mr(ptr %a, i8 noundef %b) {
+; CHECK-LABEL: and8mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb %sil, (%rdi), %al
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, %b
+ ret i8 %and
+}
+
+define i16 @and16mr(ptr %a, i16 noundef %b) {
+; CHECK-LABEL: and16mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw %si, (%rdi), %ax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, %b
+ ret i16 %and
+}
+
+define i32 @and32mr(ptr %a, i32 noundef %b) {
+; CHECK-LABEL: and32mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, (%rdi), %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, %b
+ ret i32 %and
+}
+
+define i64 @and64mr(ptr %a, i64 noundef %b) {
+; CHECK-LABEL: and64mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, (%rdi), %rax
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, %b
+ ret i64 %and
+}
+
+define i16 @and16mi8(ptr %a) {
+; CHECK-LABEL: and16mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzwl (%rdi), %eax
+; CHECK-NEXT: andl $123, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 123
+ ret i16 %and
+}
+
+define i32 @and32mi8(ptr %a) {
+; CHECK-LABEL: and32mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, (%rdi), %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123
+ ret i32 %and
+}
+
+define i64 @and64mi8(ptr %a) {
+; CHECK-LABEL: and64mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq (%rdi), %rax
+; CHECK-NEXT: andl $123, %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123
+ ret i64 %and
+}
+
+define i8 @and8mi(ptr %a) {
+; CHECK-LABEL: and8mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, (%rdi), %al
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, 123
+ ret i8 %and
+}
+
+define i16 @and16mi(ptr %a) {
+; CHECK-LABEL: and16mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzwl (%rdi), %eax
+; CHECK-NEXT: andl $1234, %eax # imm = 0x4D2
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 1234
+ ret i16 %and
+}
+
+define i32 @and32mi(ptr %a) {
+; CHECK-LABEL: and32mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, (%rdi), %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123456
+ ret i32 %and
+}
+
+define i64 @and64mi(ptr %a) {
+; CHECK-LABEL: and64mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq (%rdi), %rax
+; CHECK-NEXT: andl $123456, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123456
+ ret i64 %and
+}
+
+ at d64 = dso_local global i64 0
+
+define i1 @andflag8rr(i8 %a, i8 %b) {
+; CHECK-LABEL: andflag8rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notb %sil, %al
+; CHECK-NEXT: andb %al, %dil, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i8 %b, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16rr(i16 %a, i16 %b) {
+; CHECK-LABEL: andflag16rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notl %esi, %eax
+; CHECK-NEXT: andw %ax, %di, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 %b, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32rr(i32 %a, i32 %b) {
+; CHECK-LABEL: andflag32rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl %esi, %edi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, %b ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64rr(i64 %a, i64 %b) {
+; CHECK-LABEL: andflag64rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq %rsi, %rdi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, %b ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag8rm(ptr %ptr, i8 %b) {
+; CHECK-LABEL: andflag8rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notb %sil, %al
+; CHECK-NEXT: andb (%rdi), %al, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i8, ptr %ptr
+ %xor = xor i8 %b, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16rm(ptr %ptr, i16 %b) {
+; CHECK-LABEL: andflag16rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notl %esi, %eax
+; CHECK-NEXT: andw (%rdi), %ax, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i16, ptr %ptr
+ %xor = xor i16 %b, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32rm(ptr %ptr, i32 %b) {
+; CHECK-LABEL: andflag32rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl (%rdi), %esi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i32, ptr %ptr
+ %v0 = and i32 %a, %b ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64rm(ptr %ptr, i64 %b) {
+; CHECK-LABEL: andflag64rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq (%rdi), %rsi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i64, ptr %ptr
+ %v0 = and i64 %a, %b ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag8ri(i8 %a) {
+; CHECK-LABEL: andflag8ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $-124, %dil, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i8 123, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16ri(i16 %a) {
+; CHECK-LABEL: andflag16ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andw $-1235, %di, %cx # imm = 0xFB2D
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 1234, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32ri(i32 %a) {
+; CHECK-LABEL: andflag32ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl $123456, %edi, %ecx # imm = 0x1E240
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, 123456 ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64ri(i64 %a) {
+; CHECK-LABEL: andflag64ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq $123456, %rdi, %rcx # imm = 0x1E240
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, 123456 ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16ri8(i16 %a) {
+; CHECK-LABEL: andflag16ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andw $-124, %di, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 123, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32ri8(i32 %a) {
+; CHECK-LABEL: andflag32ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl $123, %edi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, 123 ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64ri8(i64 %a) {
+; CHECK-LABEL: andflag64ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq $123, %rdi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, 123 ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define void @and8mr_legacy(ptr %a, i8 noundef %b) {
+; CHECK-LABEL: and8mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb %sil, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, %b
+ store i8 %and, ptr %a
+ ret void
+}
+
+define void @and16mr_legacy(ptr %a, i16 noundef %b) {
+; CHECK-LABEL: and16mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw %si, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, %b
+ store i16 %and, ptr %a
+ ret void
+}
+
+define void @and32mr_legacy(ptr %a, i32 noundef %b) {
+; CHECK-LABEL: and32mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, %b
+ store i32 %and, ptr %a
+ ret void
+}
+
+define void @and64mr_legacy(ptr %a, i64 noundef %b) {
+; CHECK-LABEL: and64mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, %b
+ store i64 %and, ptr %a
+ ret void
+}
+
+define void @and8mi_legacy(ptr %a) {
+; CHECK-LABEL: and8mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, 123
+ store i8 %and, ptr %a
+ ret void
+}
+
+define void @and16mi_legacy(ptr %a) {
+; CHECK-LABEL: and16mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw $1234, (%rdi) # imm = 0x4D2
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 1234
+ store i16 %and, ptr %a
+ ret void
+}
+
+define void @and32mi_legacy(ptr %a) {
+; CHECK-LABEL: and32mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, (%rdi) # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123456
+ store i32 %and, ptr %a
+ ret void
+}
+
+define void @and64mi_legacy(ptr %a) {
+; CHECK-LABEL: and64mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq $123456, (%rdi) # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123456
+ store i64 %and, ptr %a
+ ret void
+}
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