[llvm] [X86][APX] Avoid generating illegal MI_ND ndd instructions (PR #78233)

[via llvm-commits]

================
@@ -7251,6 +7251,41 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
       MI.getOpcode() != X86::ADD64rr)
     return nullptr;
 
+  // MI_ND Instructions with 32 bit imm would exceed maximum code length if they
+  // need segment register prefix.
+  if (MOs.size() == X86::AddrNumOperands &&
+      (MOs[4].getReg() == X86::GS || MOs[4].getReg() == X86::FS ||
+       MOs[4].getReg() == X86::SS))
+    switch (MI.getOpcode()) {
+    default:
+      break;
+    case X86::ADD32ri_ND:
+    case X86::ADD64ri32_ND:
+    case X86::ADD32ri_NF_ND:
+    case X86::ADD64ri32_NF_ND:
+    case X86::SUB32ri_ND:
+    case X86::SUB64ri32_ND:
+    case X86::SUB32ri_NF_ND:
+    case X86::SUB64ri32_NF_ND:
+    case X86::AND32ri_ND:
+    case X86::AND64ri32_ND:
+    case X86::AND32ri_NF_ND:
+    case X86::AND64ri32_NF_ND:
+    case X86::XOR32ri_ND:
+    case X86::XOR64ri32_ND:
+    case X86::XOR32ri_NF_ND:
+    case X86::XOR64ri32_NF_ND:
+    case X86::OR32ri_ND:
+    case X86::OR64ri32_ND:
+    case X86::OR32ri_NF_ND:
+    case X86::OR64ri32_NF_ND:
+    case X86::ADC32ri_ND:
+    case X86::ADC64ri32_ND:
+    case X86::SBB32ri_ND:
+    case X86::SBB64ri32_ND:
+      return nullptr;
----------------
XinWang10 wrote:

Not all tested, ADC and SUB tests could test this, they generate MI_ND from mem fold.

https://github.com/llvm/llvm-project/pull/78233