[llvm] ab33c0b - [LSR] Add test showing incorrectly adding nuw with #77827.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2024-01-15T21:31:28Z
New Revision: ab33c0b96e26430b22e152cb6ecbab54dd2cfa41

URL: https://github.com/llvm/llvm-project/commit/ab33c0b96e26430b22e152cb6ecbab54dd2cfa41
DIFF: https://github.com/llvm/llvm-project/commit/ab33c0b96e26430b22e152cb6ecbab54dd2cfa41.diff

LOG: [LSR] Add test showing incorrectly adding nuw with #77827.

Extra test for https://github.com/llvm/llvm-project/pull/77827, where
NUW gets added the AddRec due to the BTC being 0.

Added: 
    llvm/test/Transforms/LoopStrengthReduce/rewrite-to-add-neg-1-expansion-flags.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopStrengthReduce/rewrite-to-add-neg-1-expansion-flags.ll b/llvm/test/Transforms/LoopStrengthReduce/rewrite-to-add-neg-1-expansion-flags.ll
new file mode 100644
index 000000000000000..ac0c765d95cf8ef
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/rewrite-to-add-neg-1-expansion-flags.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8"
+
+define i32 @btc_0(ptr %a0) {
+; CHECK-LABEL: define i32 @btc_0(
+; CHECK-SAME: ptr [[A0:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 1, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[V1:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[V8:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[V2:%.*]] = load i32, ptr [[A0]], align 4
+; CHECK-NEXT:    [[V3:%.*]] = add nsw i32 [[V1]], 1
+; CHECK-NEXT:    [[V4:%.*]] = srem i32 [[V2]], 3
+; CHECK-NEXT:    [[V5:%.*]] = icmp ne i32 [[V4]], 0
+; CHECK-NEXT:    [[V6:%.*]] = sub nsw i32 0, [[V2]]
+; CHECK-NEXT:    [[V7:%.*]] = select i1 [[V5]], i32 [[V6]], i32 [[V2]]
+; CHECK-NEXT:    [[V8]] = mul nsw i32 [[V3]], [[V7]]
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0
+; CHECK-NEXT:    br i1 [[EC]], label [[B2:%.*]], label [[LOOP]]
+; CHECK:       b2:
+; CHECK-NEXT:    [[RES:%.*]] = phi i32 [ [[V8]], [[LOOP]] ]
+; CHECK-NEXT:    br label [[EXIT:%.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+  %v1 = phi i32 [ 0, %entry ], [ %v8, %loop ]
+  %v2 = load i32, ptr %a0, align 4
+  %v3 = add nsw i32 %v1, 1
+  %v4 = srem i32 %v2, 3
+  %v5 = icmp ne i32 %v4, 0
+  %v6 = sub nsw i32 0, %v2
+  %v7 = select i1 %v5, i32 %v6, i32 %v2
+  %v8 = mul nsw i32 %v3, %v7
+  %iv.next = add nsw i32 %iv, 1
+  %ec = icmp eq i32 %iv.next, 1
+  br i1 %ec, label %b2, label %loop
+
+b2:
+  %res = phi i32 [ %v8, %loop ]
+  br label %exit
+
+exit:
+  ret i32 %res
+}