[llvm] [RISCV] Implement Intrinsics and CodeGen Support for XCValu Extension… (PR #78138)

[Craig Topper via llvm-commits]

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@@ -547,6 +563,74 @@ bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
                              RISCV::ADDI);
 }
 
+bool RISCVExpandPseudo::expandCoreVClip(llvm::MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator MBBI) {
+  DebugLoc DL = MBBI->getDebugLoc();
+  Register DstReg = MBBI->getOperand(0).getReg();
+  Register I = MBBI->getOperand(1).getReg();
+  uint64_t J = MBBI->getOperand(2).getImm();
+
+  unsigned Opcode = MBBI->getOpcode() == RISCV::CV_CLIPU_PSEUDO
+                        ? RISCV::CV_CLIPU
+                        : RISCV::CV_CLIP;
+  const MCInstrDesc &Desc = TII->get(Opcode);
+  BuildMI(MBB, MBBI, DL, Desc, DstReg)
+      .addReg(I)
+      .addImm(Log2_32_Ceil(J + 1) + 1);
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topperc wrote:

Why do we need a pseudo instruction? Can't we use an SDNodeXForm to convert the immediate?

https://github.com/llvm/llvm-project/pull/78138