[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Jun Wang via llvm-commits]

================
@@ -2831,8 +2831,13 @@ SDValue SITargetLowering::LowerFormalArguments(
       RC = &AMDGPU::VGPR_32RegClass;
     else if (AMDGPU::SGPR_32RegClass.contains(Reg))
       RC = &AMDGPU::SGPR_32RegClass;
-    else
-      llvm_unreachable("Unexpected register class in LowerFormalArguments!");
+    else {
+      if (VT == MVT::i1 && Subtarget->isWave64())
----------------
jwanggit86 wrote:

Complete MIR can be found above. The two relevant lines are:
```
%3:vreg_1 = COPY $sgpr0_sgpr1
%5:sreg_64_xexec = COPY %3:vreg_1
```
Note that the dest reg for the COPY from $sgpr0_sgpr1 is vreg_1, not sreg_64_xexec. This insn will trigger the assert in SILowerI1Copies. The patch checks for this and skip the insn to avoid the assert.

https://github.com/llvm/llvm-project/pull/72461