[llvm] [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU (PR #77631)

[Matt Arsenault via llvm-commits]

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@@ -2,6 +2,13 @@
 ;
 ; NVPTX produces a different order of the BBs
 ; XFAIL: target=nvptx{{.*}}
+; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
+; pipeline. This test prematurely stops at the first one, which doesn't cleanup
+; the virtual register map and cause an assertion failure. Ideally we can solve
+; this by teaching `-stop-after` how to stop at the last instance of a Pass,
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arsenm wrote:

You can use -stop-after=passname,1 to skip to the next instance 

https://github.com/llvm/llvm-project/pull/77631