[llvm] c32d02e - [AArch64][GlobalISel] Fix not extending GPR32->GPR64 result of anyext indexed load.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2024-01-15T08:22:39-08:00
New Revision: c32d02efd2564891b8edeef20083c3b5055c7cbd

URL: https://github.com/llvm/llvm-project/commit/c32d02efd2564891b8edeef20083c3b5055c7cbd
DIFF: https://github.com/llvm/llvm-project/commit/c32d02efd2564891b8edeef20083c3b5055c7cbd.diff

LOG: [AArch64][GlobalISel] Fix not extending GPR32->GPR64 result of anyext indexed load.

Was causing assertions to fail.

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-anyext-indexed-load-crash.ll

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 4e110200c30a66..eabbe688a1c764 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -114,6 +114,21 @@ class GIndexedExtLoad : public GIndexedLoad {
   }
 };
 
+/// Represents either G_INDEXED_LOAD, G_INDEXED_ZEXTLOAD or G_INDEXED_SEXTLOAD.
+class GIndexedAnyExtLoad : public GIndexedLoad {
+public:
+  static bool classof(const MachineInstr *MI) {
+    switch (MI->getOpcode()) {
+    case TargetOpcode::G_INDEXED_LOAD:
+    case TargetOpcode::G_INDEXED_ZEXTLOAD:
+    case TargetOpcode::G_INDEXED_SEXTLOAD:
+      return true;
+    default:
+      return false;
+    }
+  }
+};
+
 /// Represents a G_ZEXTLOAD.
 class GIndexedZExtLoad : GIndexedExtLoad {
 public:

diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index a4ace6cce46342..8344e79f78e1eb 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5610,7 +5610,7 @@ MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImmFP(
 
 bool AArch64InstructionSelector::selectIndexedExtLoad(
     MachineInstr &MI, MachineRegisterInfo &MRI) {
-  auto &ExtLd = cast<GIndexedExtLoad>(MI);
+  auto &ExtLd = cast<GIndexedAnyExtLoad>(MI);
   Register Dst = ExtLd.getDstReg();
   Register WriteBack = ExtLd.getWritebackReg();
   Register Base = ExtLd.getBaseReg();
@@ -5697,10 +5697,6 @@ bool AArch64InstructionSelector::selectIndexedExtLoad(
 
 bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
                                                    MachineRegisterInfo &MRI) {
-  // TODO: extending loads.
-  if (isa<GIndexedExtLoad>(MI))
-    return false;
-
   auto &Ld = cast<GIndexedLoad>(MI);
   Register Dst = Ld.getDstReg();
   Register WriteBack = Ld.getWritebackReg();
@@ -5710,6 +5706,9 @@ bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
          "Unexpected type for indexed load");
   unsigned MemSize = Ld.getMMO().getMemoryType().getSizeInBytes();
 
+  if (MemSize < MRI.getType(Dst).getSizeInBytes())
+    return selectIndexedExtLoad(MI, MRI);
+
   unsigned Opc = 0;
   if (Ld.isPre()) {
     static constexpr unsigned GPROpcodes[] = {

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-anyext-indexed-load-crash.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-anyext-indexed-load-crash.ll
new file mode 100644
index 00000000000000..487577c0383baa
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-anyext-indexed-load-crash.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel %s -o - | FileCheck %s
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-macosx14.0.0"
+
+define void @test() {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    sub sp, sp, #32
+; CHECK-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset w30, -8
+; CHECK-NEXT:    .cfi_offset w29, -16
+; CHECK-NEXT:    mov x0, xzr
+; CHECK-NEXT:    mov x1, xzr
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    ldr w9, [x8], #8
+; CHECK-NEXT:    str x8, [x0]
+; CHECK-NEXT:    str x9, [sp]
+; CHECK-NEXT:    bl _sprintf
+; CHECK-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-NEXT:    add sp, sp, #32
+; CHECK-NEXT:    ret
+entry:
+  %0 = va_arg ptr null, i32
+  %sprintf1776 = tail call i32 (ptr, ptr, ...) @sprintf(ptr null, ptr null, i32 %0)
+  ret void
+}
+
+declare i32 @sprintf(ptr, ptr, ...)